GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

AMD Hudson: Add support for the SD controller 

This patch provides the correct SD controller timings for
the Family16 device. It also will remove the SD controller
from PCI space when device 0:14.7 is set to off in devicetree.
This was tested on a AMD Parmer board and a AMD G-series SOC
reference board. The settings were found in the AMD
Hudson2 RRG and family16 BKGD.

Change-Id: I6d7e7997ddc39802ab75dc8a211ed29f028c0471
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/3348
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Dave Frodin 2013-05-31 08:15:57 -06:00 committed by Stefan Reinauer
parent 9029265cf5
commit ea90963666
5 changed files with 104 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/include/device/pci_ids.h
View File

@ -361,6 +361,8 @@
#define PCI_DEVICE_ID_ATI_SB900_USB_19_2 0x7808
#define PCI_DEVICE_ID_ATI_SB900_USB_20_5 0x7809
#define PCI_DEVICE_ID_ATI_SB900_GEC 0x7806
#define PCI_DEVICE_ID_AMD_HUDSON_SD 0x7806
#define PCI_DEVICE_ID_AMD_YANGTZE_SD 0x7813
#define PCI_DEVICE_ID_ATI_RS690_HT 0x7910
#define PCI_DEVICE_ID_ATI_RS740_HT 0x7911

2
src/southbridge/amd/agesa/hudson/Makefile.inc
View File

@ -8,6 +8,8 @@ ramstage-y += sata.c
ramstage-y += hda.c
ramstage-y += pci.c
ramstage-y += pcie.c
ramstage-y += sd.c
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c
ramstage-y += reset.c
romstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c

1
src/southbridge/amd/agesa/hudson/chip.h
View File

@ -28,6 +28,7 @@ struct southbridge_amd_agesa_hudson_config
u32 boot_switch_sata_ide : 1;
u32 hda_viddid;
u8 gpp_configuration;
u8 sd_mode;
#endif
};

30
src/southbridge/amd/agesa/hudson/hudson.c
View File

@ -100,6 +100,36 @@ u8 pm2_ioread(u8 reg)
void hudson_enable(device_t dev)
{
printk(BIOS_DEBUG, "hudson_enable()\n");
switch (dev->path.pci.devfn) {
case (0x14 << 3) | 7: /* 0:14.7 SD */
if (dev->enabled == 0) {
// read the VENDEV ID
device_t sd_dev = dev_find_slot( 0, PCI_DEVFN( 0x14, 7));
u32 sd_device_id = pci_read_config32( sd_dev, 0) >> 16;
/* turn off the SDHC controller in the PM reg */
u8 sd_tmp;
if (sd_device_id == PCI_DEVICE_ID_AMD_HUDSON_SD) {
outb(0xE7, PM_INDEX);
sd_tmp = inb(PM_DATA);
sd_tmp &= ~(1 << 0);
outb(sd_tmp, PM_DATA);
}
else if (sd_device_id == PCI_DEVICE_ID_AMD_YANGTZE_SD) {
outb(0xE8, PM_INDEX);
sd_tmp = inb(PM_DATA);
sd_tmp &= ~(1 << 0);
outb(sd_tmp, PM_DATA);
}
/* remove device 0:14.7 from PCI space */
outb(0xD3, PM_INDEX);
sd_tmp = inb(PM_DATA);
sd_tmp &= ~(1 << 6);
outb(sd_tmp, PM_DATA);
}
break;
default:
break;
}
}
struct cbmem_entry *get_cbmem_toc(void)

69
src/southbridge/amd/agesa/hudson/sd.c Normal file
View File

@ -0,0 +1,69 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <device/device.h>
#include <delay.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <arch/io.h>
#include "hudson.h"
static void sd_init(struct device *dev)
{
u32 stepping;
stepping = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xFC);
struct southbridge_amd_agesa_hudson_config *sd_chip =
(struct southbridge_amd_agesa_hudson_config *)(dev->chip_info);
if (sd_chip->sd_mode == 3) { /* SD 3.0 mode */
pci_write_config32(dev, 0xA4, 0x31FEC8B2);
pci_write_config32(dev, 0xA8, 0x00002503);
pci_write_config32(dev, 0xB0, 0x02180C19);
pci_write_config32(dev, 0xD0, 0x0000078B);
}
else { /* SD 2.0 mode */
if ((stepping & 0x0000000F) == 0) { /* Stepping A0 */
pci_write_config32(dev, 0xA4, 0x31DE32B2);
pci_write_config32(dev, 0xB0, 0x01180C19);
pci_write_config32(dev, 0xD0, 0x0000058B);
}
else { /* Stepping >= A1 */
pci_write_config32(dev, 0xA4, 0x31FE3FB2);
pci_write_config32(dev, 0xB0, 0x01180C19);
pci_write_config32(dev, 0xD0, 0x0000078B);
}
}
}
static struct device_operations sd_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = sd_init,
.scan_bus = 0,
};
static const struct pci_driver sd_driver __pci_driver = {
.ops = &sd_ops,
.vendor = PCI_VENDOR_ID_AMD,
.device = PCI_DEVICE_ID_AMD_YANGTZE_SD,
};