cpu/x86/mtrr.h: Rename CORE2 alternative SMRR registers
It is too easy to confuse those with IA32_SMRR_PHYS_x registers. Change-Id: Ice02ab6c0315a2be14ef110ede506262e3c0a4d5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46896 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -59,8 +59,8 @@ static void write_smrr_alt(struct smm_relocation_params *relo_params)
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printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
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printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
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relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
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relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
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wrmsr(MSR_SMRR_PHYS_BASE, relo_params->smrr_base);
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wrmsr(CORE2_SMRR_PHYS_BASE, relo_params->smrr_base);
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wrmsr(MSR_SMRR_PHYS_MASK, relo_params->smrr_mask);
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wrmsr(CORE2_SMRR_PHYS_MASK, relo_params->smrr_mask);
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}
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}
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static void fill_in_relocation_params(struct smm_relocation_params *params)
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static void fill_in_relocation_params(struct smm_relocation_params *params)
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@ -31,9 +31,10 @@
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#define IA32_SMRR_PHYS_MASK 0x1f3
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#define IA32_SMRR_PHYS_MASK 0x1f3
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#define SMRR_PHYS_MASK_LOCK (1 << 10)
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#define SMRR_PHYS_MASK_LOCK (1 << 10)
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/* Specific to model_6fx and model_1067x */
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/* Specific to model_6fx and model_1067x.
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#define MSR_SMRR_PHYS_BASE 0xa0
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These are named MSR_SMRR_PHYSBASE in the SDM. */
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#define MSR_SMRR_PHYS_MASK 0xa1
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#define CORE2_SMRR_PHYS_BASE 0xa0
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#define CORE2_SMRR_PHYS_MASK 0xa1
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#define MTRR_PHYS_BASE(reg) (0x200 + 2 * (reg))
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#define MTRR_PHYS_BASE(reg) (0x200 + 2 * (reg))
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#define MTRR_PHYS_MASK(reg) (MTRR_PHYS_BASE(reg) + 1)
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#define MTRR_PHYS_MASK(reg) (MTRR_PHYS_BASE(reg) + 1)
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