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cpu/x86/mtrr.h: Rename CORE2 alternative SMRR registers 

It is too easy to confuse those with IA32_SMRR_PHYS_x registers.

Change-Id: Ice02ab6c0315a2be14ef110ede506262e3c0a4d5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46896
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans 2020-10-28 19:30:36 +01:00 committed by Patrick Georgi
parent 94fe086a06
commit eaaa549e4a
2 changed files with 6 additions and 5 deletions
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4
src/cpu/intel/smm/gen1/smmrelocate.c
View File

@ -59,8 +59,8 @@ static void write_smrr_alt(struct smm_relocation_params *relo_params)
printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
wrmsr(MSR_SMRR_PHYS_BASE, relo_params->smrr_base);
wrmsr(MSR_SMRR_PHYS_MASK, relo_params->smrr_mask);
wrmsr(CORE2_SMRR_PHYS_BASE, relo_params->smrr_base);
wrmsr(CORE2_SMRR_PHYS_MASK, relo_params->smrr_mask);
}
static void fill_in_relocation_params(struct smm_relocation_params *params)

7
src/include/cpu/x86/mtrr.h
View File

@ -31,9 +31,10 @@
#define IA32_SMRR_PHYS_MASK 0x1f3
#define SMRR_PHYS_MASK_LOCK (1 << 10)
/* Specific to model_6fx and model_1067x */
#define MSR_SMRR_PHYS_BASE 0xa0
#define MSR_SMRR_PHYS_MASK 0xa1
/* Specific to model_6fx and model_1067x.
These are named MSR_SMRR_PHYSBASE in the SDM. */
#define CORE2_SMRR_PHYS_BASE 0xa0
#define CORE2_SMRR_PHYS_MASK 0xa1
#define MTRR_PHYS_BASE(reg) (0x200 + 2 * (reg))
#define MTRR_PHYS_MASK(reg) (MTRR_PHYS_BASE(reg) + 1)