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mb/google/dedede/beadrix: Update PCIe and SATA pins for Realtek RTL8822CE suspend 

To make sure Realtek RTL8822CE suspend stress test smoothly, we remove
1c.7 as wireless LAN (WLAN) connects the signal PCIE_4 and it will map
to 1c.7. refer to Intel Simon comment (https://partnerissuetracker.corp.google.com/issues/230386474#comment12),
as well as, remove redundant 17.0 and 1c.6 that both are described by
baseboard/devicetree.cb

BRANCH=dedede
BUG=b:230386474
TEST=on beadrix, verified by Realtek RTL8822CE can run suspend stress
test properly.

Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: Ib418eed57f07afaa6b397b42a057808eab142f7a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivan Chen <yulunchen@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
This commit is contained in:
Teddy Shih 2022-05-09 16:10:18 +08:00 committed by Felix Held
parent c2461a174d
commit eb0c90aec5
1 changed files with 0 additions and 3 deletions
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3
src/mainboard/google/dedede/variants/beadrix/overridetree.cb
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@ -130,7 +130,6 @@ chip soc/intel/jasperlake
device i2c 15 on end device i2c 15 on end
end end
end # I2C 0 end # I2C 0
device pci 17.0 off end # SATA. Baseboard/devicetree.cb is off
device pci 19.0 on device pci 19.0 on
chip drivers/i2c/generic chip drivers/i2c/generic
register "hid" = ""10EC5682"" register "hid" = ""10EC5682""
@ -198,8 +197,6 @@ chip soc/intel/jasperlake
device i2c 28 on end device i2c 28 on end
end end
end # I2C 5 end # I2C 5
device pci 1c.6 off end # PCI Express Root Port 7 / SATA_0. Baseboard/devicetree.cb is off
device pci 1c.7 off end # PCI Express Root Port 8 / SATA_1
device pci 1f.3 on device pci 1f.3 on
chip drivers/generic/max98357a chip drivers/generic/max98357a
register "hid" = ""MX98360A"" register "hid" = ""MX98360A""