GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

rockchip/rk3399: Enable ramstage compression, shuffle around memlayout 

Since we now have so much more room for activities in our romstage SRAM
section, we can easily fit the LZMA decompressor to enable ramstage
compression. Also shuffle around memlayout sections a little more to
make use of unused space, and balance out leftover memory so that all
sections that might need future expansion have a reasonable amount.

Change-Id: I47f2d03e520fc3103ef04257b4ba7e93874b8956
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16334
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Julius Werner 2016-07-29 12:30:50 -07:00
parent 329031fded
commit eb131f30a3
2 changed files with 7 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/soc/rockchip/rk3399/Kconfig
View File

@ -11,7 +11,6 @@ config SOC_ROCKCHIP_RK3399
select DRIVERS_UART_8250MEM_32 select DRIVERS_UART_8250MEM_32
select GENERIC_UDELAY select GENERIC_UDELAY
select HAVE_MONOTONIC_TIMER select HAVE_MONOTONIC_TIMER
select UNCOMPRESSED_RAMSTAGE
select UART_OVERRIDE_REFCLK select UART_OVERRIDE_REFCLK
if SOC_ROCKCHIP_RK3399 if SOC_ROCKCHIP_RK3399

14
src/soc/rockchip/rk3399/include/soc/memlayout.ld
View File

@ -25,13 +25,13 @@ SECTIONS
FRAMEBUFFER(0x10200000, 8M) FRAMEBUFFER(0x10200000, 8M)
SRAM_START(0xFF8C0000) SRAM_START(0xFF8C0000)
BOOTBLOCK(0xFF8C2004, 31K - 4) PRERAM_CBMEM_CONSOLE(0xFF8C0000, 7K)
PRERAM_CBMEM_CONSOLE(0xFF8C9C00, 5K) TIMESTAMP(0xFF8C1C00, 1K)
BOOTBLOCK(0xFF8C2004, 36K - 4)
PRERAM_CBFS_CACHE(0xFF8CB000, 4K) PRERAM_CBFS_CACHE(0xFF8CB000, 4K)
TTB(0xFF8CC000, 32K) TTB(0xFF8CC000, 24K)
OVERLAP_VERSTAGE_ROMSTAGE(0xFF8D4000, 75K) OVERLAP_VERSTAGE_ROMSTAGE(0xFF8D2000, 92K)
VBOOT2_WORK(0XFF8E6C00, 12K) VBOOT2_WORK(0XFF8E9000, 12K)
TIMESTAMP(0xFF8E9C00, 1K) STACK(0xFF8EC000, 16K)
STACK(0xFF8EA000, 24K)
SRAM_END(0xFF8F0000) SRAM_END(0xFF8F0000)
} }