mb/siemens/chili: do UART pad configuration at board-level

UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index. Thus,
add the corresponding pads to a bootblock gpio table for the board as a
first step. Common UART pad config code then gets dropped in CB:48829.

Change-Id: Iad40b6315a29e7aea612a3e1a169372d296d1d6c
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49443
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/siemens/chili/Makefile.inc

@@ -2,6 +2,8 @@
 
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
 
+bootblock-y += bootblock.c
+
 romstage-y += romstage.c
 
 ramstage-y += mainboard.c

src/mainboard/siemens/chili/bootblock.c

@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <variant/gpio.h>
+
+__weak void variant_configure_early_gpios(void) {}
+
+void bootblock_mainboard_early_init(void)
+{
+	variant_configure_early_gpios();
+}

src/mainboard/siemens/chili/include/variant/gpio.h

@@ -3,6 +3,7 @@
 #ifndef VARIANT_GPIO_H
 #define VARIANT_GPIO_H
 
+void variant_configure_early_gpios(void);
 void variant_configure_gpios(void);
 
 #endif

src/mainboard/siemens/chili/variants/chili/Makefile.inc

@@ -1,5 +1,7 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
+bootblock-y += gpio_early.c
+
 romstage-y += romstage.c
 romstage-y += gpio.c
 

src/mainboard/siemens/chili/variants/chili/gpio_early.c

@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/gpio.h>
+#include <variant/gpio.h>
+
+static const struct pad_config early_gpio_table[] = {
+/* GPP_C8    UART0A_RXD           0x0000005044000702 */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
+/* GPP_C9    UART0A_TXD           0x0000005144000700 */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
+/* GPP_C20   UART2_RXD            0x0000005c44000500 */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+/* GPP_C21   UART2_TXD            0x0000005d44000600 */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+};
+
+void variant_configure_early_gpios(void)
+{
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}