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amd/torpedo cimx/sb900: Fix include directory 

Change-Id: Ie472092f8926231f4e1bd1fb12839b532b4ad158
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/23279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2018-01-15 17:52:58 +02:00
parent 63278ab07d
commit eb7e6b5c81
2 changed files with 9 additions and 2 deletions
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2
src/mainboard/amd/torpedo/BiosCallOuts.c
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@ -18,7 +18,7 @@
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include "Hudson-2.h"
#include <stdlib.h>
#include <southbridge/amd/cimx/sb700/gpio_oem.h>
#include <southbridge/amd/cimx/sb900/gpio_oem.h>
static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr);
static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr);

9
src/southbridge/amd/cimx/sb900/gpio_oem.h
View File

@ -3,7 +3,7 @@
/* Hudson-2 ACPI PmIO Space Define */
#define SB_ACPI_BASE_ADDRESS 0x0400
#define ACPI_MMIO_BASE ((u8 *)0xFED80000)
#define VACPI_MMIO_BASE ((u8 *)0xFED80000)
#define SB_CFG_BASE 0x000 // DWORD
#define GPIO_BASE 0x100 // BYTE
#define SMI_BASE 0x200 // DWORD
@ -43,4 +43,11 @@
#define Mmio32( BaseAddr, Register ) \
*Mmio32Ptr( BaseAddr, Register )
#define SB_GPIO_REG01 1
#define SB_GPIO_REG02 2
#define SB_GPIO_REG15 15
#define SB_GPIO_REG24 24
#define SB_GPIO_REG25 25
#define SB_GPIO_REG27 27
#endif