YhLu's changes to resolve several memory and other problems.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1036 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
parent
feaa75960c
commit
ebb645a9fb
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@ -411,6 +411,10 @@
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#define PCI_DEVICE_ID_AMD_8111_SMB 0x746a
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#define PCI_DEVICE_ID_AMD_8111_SMB 0x746a
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#define PCI_DEVICE_ID_AMD_8111_ACPI 0x746b
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#define PCI_DEVICE_ID_AMD_8111_ACPI 0x746b
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#define PCI_DEVICE_ID_AMD_8111_USB2 0x7463
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#define PCI_DEVICE_ID_AMD_8131_PCIX 0x7450
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#define PCI_DEVICE_ID_AMD_8131_IOAPIC 0x7451
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#define PCI_VENDOR_ID_TRIDENT 0x1023
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#define PCI_VENDOR_ID_TRIDENT 0x1023
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#define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX 0x2000
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#define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX 0x2000
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#define PCI_DEVICE_ID_TRIDENT_4DWAVE_NX 0x2001
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#define PCI_DEVICE_ID_TRIDENT_4DWAVE_NX 0x2001
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@ -1,437 +1,211 @@
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#define ASSEMBLY 1
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#define ASSEMBLY 1
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#include <stdint.h>
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#include <stdint.h>
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#include <device/pci_def.h>
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#include <device/pci_def.h>
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#include "arch/romcc_io.h"
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#include <cpu/p6/apic.h>
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#include <arch/io.h>
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#include <arch/romcc_io.h>
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#include "pc80/serial.c"
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#include "pc80/serial.c"
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#include "arch/i386/lib/console.c"
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#include "arch/i386/lib/console.c"
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#include "ram/ramtest.c"
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#include "ram/ramtest.c"
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#include "northbridge/amd/amdk8/early_ht.c"
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#include "northbridge/amd/amdk8/early_ht.c"
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#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
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#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
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#include "northbridge/amd/amdk8/raminit.h"
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#include "northbridge/amd/amdk8/raminit.h"
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/*
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#include "cpu/k8/apic_timer.c"
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#warning "FIXME move these delay functions somewhere more appropriate"
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#include "lib/delay.c"
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#warning "FIXME use the apic timer instead it needs no calibration on an Opteron it runs at 200Mhz"
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#include "cpu/p6/boot_cpu.c"
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static void print_clock_multiplier(void)
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#include "northbridge/amd/amdk8/reset_test.c"
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{
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#include "debug.c"
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msr_t msr;
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print_debug("clock multipler: 0x");
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msr = rdmsr(0xc0010042);
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print_debug_hex32(msr.lo & 0x3f);
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print_debug(" = 0x");
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print_debug_hex32(((msr.lo & 0x3f) + 8) * 100);
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print_debug("Mhz\r\n");
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}
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static unsigned usecs_to_ticks(unsigned usecs)
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static void memreset_setup(void)
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{
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{
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#warning "FIXME make usecs_to_ticks work properly"
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/* Set the memreset low */
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#if 1
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return usecs *2000;
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#else
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// This can only be done if cpuid says fid changing is supported
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// I need to look up the base frequency another way for other
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// cpus. Is it worth dedicating a global register to this?
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// Are the PET timers useable for this purpose?
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msr_t msr;
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msr = rdmsr(0xc0010042);
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return ((msr.lo & 0x3f) + 8) * 100 *usecs;
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#endif
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}
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static void init_apic_timer(void)
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{
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volatile uint32_t *apic_reg = (volatile uint32_t *)0xfee00000;
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uint32_t start, end;
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// Set the apic timer to no interrupts and periodic mode
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apic_reg[0x320 >> 2] = (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0);
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// Set the divider to 1, no divider
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apic_reg[0x3e0 >> 2] = (1 << 3) | 3;
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// Set the initial counter to 0xffffffff
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apic_reg[0x380 >> 2] = 0xffffffff;
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}
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static void udelay(unsigned usecs)
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{
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#if 1
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uint32_t start, ticks;
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tsc_t tsc;
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// Calculate the number of ticks to run for
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ticks = usecs_to_ticks(usecs);
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// Find the current time
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tsc = rdtsc();
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start = tsc.lo;
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do {
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tsc = rdtsc();
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} while((tsc.lo - start) < ticks);
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#else
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volatile uint32_t *apic_reg = (volatile uint32_t *)0xfee00000;
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uint32_t start, value, ticks;
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// Calculate the number of ticks to run for
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ticks = usecs * 200;
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start = apic_reg[0x390 >> 2];
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do {
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value = apic_reg[0x390 >> 2];
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} while((start - value) < ticks);
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#endif
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}
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static void mdelay(unsigned msecs)
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{
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int i;
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for(i = 0; i < msecs; i++) {
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udelay(1000);
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}
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}
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static void delay(unsigned secs)
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{
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int i;
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for(i = 0; i < secs; i++) {
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mdelay(1000);
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}
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}
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static void memreset_setup(const struct mem_controller *ctrl)
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{
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// Set the memreset low
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
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// Ensure the BIOS has control of the memory lines
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/* Ensure the BIOS has control of the memory lines */
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
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print_debug("memreset lo\r\n");
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}
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}
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static void memreset(const struct mem_controller *ctrl)
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static void memreset(int controllers, const struct mem_controller *ctrl)
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{
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{
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udelay(800);
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udelay(800);
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// Set memreset_high
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/* Set memreset_high */
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outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
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outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
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print_debug("memreset hi\r\n");
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udelay(90);
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udelay(50);
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}
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}
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static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
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{
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/* Routing Table Node i
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*
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* F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
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* i: 0, 1, 2, 3, 4, 5, 6, 7
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*
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* [ 0: 3] Request Route
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* [0] Route to this node
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* [1] Route to Link 0
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* [2] Route to Link 1
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* [3] Route to Link 2
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* [11: 8] Response Route
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* [0] Route to this node
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* [1] Route to Link 0
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* [2] Route to Link 1
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* [3] Route to Link 2
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* [19:16] Broadcast route
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* [0] Route to this node
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* [1] Route to Link 0
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* [2] Route to Link 1
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* [3] Route to Link 2
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*/
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*/
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uint32_t ret=0x00010101; /* default row entry */
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static const unsigned int rows_2p[2][2] = {
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{ 0x00050101, 0x00010404 },
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{ 0x00010404, 0x00050101 }
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};
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if(maxnodes>2) {
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print_debug("this mainboard is only designed for 2 cpus\r\n");
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maxnodes=2;
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}
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if (!(node>=maxnodes || row>=maxnodes)) {
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ret=rows_2p[node][row];
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}
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return ret;
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}
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static inline int spd_read_byte(unsigned device, unsigned address)
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{
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return smbus_read_byte(device, address);
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}
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#include "northbridge/amd/amdk8/cpu_ldtstop.c"
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#include "southbridge/amd/amd8111/amd8111_ldtstop.c"
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#include "northbridge/amd/amdk8/raminit.c"
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#include "northbridge/amd/amdk8/raminit.c"
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#include "northbridge/amd/amdk8/coherent_ht.c"
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#include "northbridge/amd/amdk8/coherent_ht.c"
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#include "sdram/generic_sdram.c"
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#include "sdram/generic_sdram.c"
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#define NODE_ID 0x60
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static void enable_lapic(void)
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#define HT_INIT_CONTROL 0x6c
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#define HTIC_ColdR_Detect (1<<4)
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#define HTIC_BIOSR_Detect (1<<5)
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#define HTIC_INIT_Detect (1<<6)
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#define APIC_DEFAULT_BASE 0xfee00000
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#define APIC_ID 0x020
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static int boot_cpu(void)
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{
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{
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volatile unsigned long *local_apic;
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unsigned long apic_id;
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int bsp;
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int apicEn;
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msr_t msr;
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msr_t msr;
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msr = rdmsr(0x1b);
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msr = rdmsr(0x1b);
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bsp = !!(msr.lo & (1 << 8));
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msr.hi &= 0xffffff00;
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apicEn = !!(msr.lo & (1<<11));
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msr.lo &= 0x000007ff;
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if(apicEn) {
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msr.lo |= APIC_DEFAULT_BASE | (1 << 11);
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print_debug("apic enabled\r\n");
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} else {
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msr.lo |= (1<<11);
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wrmsr(0x1b, msr);
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wrmsr(0x1b, msr);
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}
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}
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apic_id = *((volatile unsigned long *)(APIC_DEFAULT_BASE+APIC_ID));
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print_debug("apic_id: ");
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print_debug_hex32(apic_id>>24);
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print_debug("\r\n");
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if (bsp) {
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static void stop_this_cpu(void)
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print_debug("Bootstrap cpu\r\n");
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} else {
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print_debug("Application processor\r\n");
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// asm("hlt"); // move to end before halt should notify BSP
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// if you start AP in coherent.c you can just stop it here
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}
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return bsp;
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}
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static int cpu_init_detected(void)
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{
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{
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unsigned long dcl;
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unsigned apicid;
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int cpu_init;
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apicid = apic_read(APIC_ID) >> 24;
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unsigned long htic;
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/* Send an APIC INIT to myself */
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apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
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apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT);
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/* Wait for the ipi send to finish */
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apic_wait_icr_idle();
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htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
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/* Deassert the APIC INIT */
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#if 0
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apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
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print_debug("htic: ");
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apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
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print_debug_hex32(htic);
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/* Wait for the ipi send to finish */
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print_debug("\r\n");
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apic_wait_icr_idle();
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if (!(htic & HTIC_ColdR_Detect)) {
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/* If I haven't halted spin forever */
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print_debug("Cold Reset.\r\n");
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for(;;) {
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}
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hlt();
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if ((htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect)) {
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print_debug("BIOS generated Reset.\r\n");
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}
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if (htic & HTIC_INIT_Detect) {
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print_debug("Init event.\r\n");
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}
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#endif
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cpu_init = (htic & HTIC_INIT_Detect);
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if (cpu_init) {
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print_debug("CPU INIT Detected.\r\n");
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}
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return cpu_init;
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}
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/*
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static void print_debug_pci_dev(unsigned dev)
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{
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print_debug("PCI: ");
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print_debug_hex8((dev >> 16) & 0xff);
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print_debug_char(':');
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print_debug_hex8((dev >> 11) & 0x1f);
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print_debug_char('.');
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print_debug_hex8((dev >> 8) & 7);
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}
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static void print_pci_devices(void)
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{
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device_t dev;
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for(dev = PCI_DEV(0, 0, 0);
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dev <= PCI_DEV(0, 0x1f, 0x7);
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dev += PCI_DEV(0,0,1)) {
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uint32_t id;
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id = pci_read_config32(dev, PCI_VENDOR_ID);
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if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
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(((id >> 16) & 0xffff) == 0xffff) ||
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(((id >> 16) & 0xffff) == 0x0000)) {
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continue;
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}
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print_debug_pci_dev(dev);
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print_debug("\r\n");
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}
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}
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}
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}
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*/
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#define FIRST_CPU 1
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/*
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#define SECOND_CPU 1
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static void dump_pci_device(unsigned dev)
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#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
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{
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int i;
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print_debug_pci_dev(dev);
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print_debug("\r\n");
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for(i = 0; i <= 255; i++) {
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unsigned char val;
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if ((i & 0x0f) == 0) {
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print_debug_hex8(i);
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print_debug_char(':');
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}
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val = pci_read_config8(dev, i);
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print_debug_char(' ');
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print_debug_hex8(val);
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if ((i & 0x0f) == 0x0f) {
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print_debug("\r\n");
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}
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}
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}
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static void dump_pci_devices(void)
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{
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device_t dev;
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for(dev = PCI_DEV(0, 0, 0);
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dev <= PCI_DEV(0, 0x1f, 0x7);
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dev += PCI_DEV(0,0,1)) {
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uint32_t id;
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id = pci_read_config32(dev, PCI_VENDOR_ID);
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if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
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(((id >> 16) & 0xffff) == 0xffff) ||
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(((id >> 16) & 0xffff) == 0x0000)) {
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continue;
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}
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dump_pci_device(dev);
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}
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}
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static void dump_spd_registers(const struct mem_controller *ctrl)
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{
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int i;
|
|
||||||
print_debug("\r\n");
|
|
||||||
for(i = 0; i < 4; i++) {
|
|
||||||
unsigned device;
|
|
||||||
device = ctrl->channel0[i];
|
|
||||||
if (device) {
|
|
||||||
int j;
|
|
||||||
print_debug("dimm: ");
|
|
||||||
print_debug_hex8(i);
|
|
||||||
print_debug(".0: ");
|
|
||||||
print_debug_hex8(device);
|
|
||||||
for(j = 0; j < 256; j++) {
|
|
||||||
int status;
|
|
||||||
unsigned char byte;
|
|
||||||
if ((j & 0xf) == 0) {
|
|
||||||
print_debug("\r\n");
|
|
||||||
print_debug_hex8(j);
|
|
||||||
print_debug(": ");
|
|
||||||
}
|
|
||||||
status = smbus_read_byte(device, j);
|
|
||||||
if (status < 0) {
|
|
||||||
print_debug("bad device\r\n");
|
|
||||||
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
byte = status & 0xff;
|
|
||||||
print_debug_hex8(byte);
|
|
||||||
print_debug_char(' ');
|
|
||||||
}
|
|
||||||
print_debug("\r\n");
|
|
||||||
}
|
|
||||||
device = ctrl->channel1[i];
|
|
||||||
if (device) {
|
|
||||||
int j;
|
|
||||||
print_debug("dimm: ");
|
|
||||||
print_debug_hex8(i);
|
|
||||||
print_debug(".1: ");
|
|
||||||
print_debug_hex8(device);
|
|
||||||
for(j = 0; j < 256; j++) {
|
|
||||||
int status;
|
|
||||||
unsigned char byte;
|
|
||||||
if ((j & 0xf) == 0) {
|
|
||||||
print_debug("\r\n");
|
|
||||||
print_debug_hex8(j);
|
|
||||||
print_debug(": ");
|
|
||||||
}
|
|
||||||
status = smbus_read_byte(device, j);
|
|
||||||
|
|
||||||
if (status < 0) {
|
|
||||||
print_debug("bad device\r\n");
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
byte = status & 0xff;
|
|
||||||
print_debug_hex8(byte);
|
|
||||||
print_debug_char(' ');
|
|
||||||
}
|
|
||||||
print_debug("\r\n");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
static void main(void)
|
static void main(void)
|
||||||
{
|
{
|
||||||
static const struct mem_controller cpu0 = {
|
/*
|
||||||
|
* GPIO28 of 8111 will control H0_MEMRESET_L
|
||||||
|
* GPIO29 of 8111 will control H1_MEMRESET_L
|
||||||
|
*/
|
||||||
|
static const struct mem_controller cpu[] = {
|
||||||
|
#if FIRST_CPU
|
||||||
|
{
|
||||||
|
.node_id = 0,
|
||||||
.f0 = PCI_DEV(0, 0x18, 0),
|
.f0 = PCI_DEV(0, 0x18, 0),
|
||||||
.f1 = PCI_DEV(0, 0x18, 1),
|
.f1 = PCI_DEV(0, 0x18, 1),
|
||||||
.f2 = PCI_DEV(0, 0x18, 2),
|
.f2 = PCI_DEV(0, 0x18, 2),
|
||||||
.f3 = PCI_DEV(0, 0x18, 3),
|
.f3 = PCI_DEV(0, 0x18, 3),
|
||||||
.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
|
.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
|
||||||
.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
|
.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
|
||||||
};
|
},
|
||||||
static const struct mem_controller cpu1 = {
|
#endif
|
||||||
|
#if SECOND_CPU
|
||||||
|
{
|
||||||
|
.node_id = 1,
|
||||||
.f0 = PCI_DEV(0, 0x19, 0),
|
.f0 = PCI_DEV(0, 0x19, 0),
|
||||||
.f1 = PCI_DEV(0, 0x19, 1),
|
.f1 = PCI_DEV(0, 0x19, 1),
|
||||||
.f2 = PCI_DEV(0, 0x19, 2),
|
.f2 = PCI_DEV(0, 0x19, 2),
|
||||||
.f3 = PCI_DEV(0, 0x19, 3),
|
.f3 = PCI_DEV(0, 0x19, 3),
|
||||||
.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
|
.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
|
||||||
.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
|
.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
|
||||||
};
|
},
|
||||||
|
|
||||||
// device_t dev;
|
|
||||||
// unsigned where;
|
|
||||||
unsigned long reg;
|
|
||||||
// dev = PCI_ADDR(0, 0x19, 0, 0x6C) & ~0xff;
|
|
||||||
// where = PCI_ADDR(0, 0x19, 0, 0x6C) & 0xff;
|
|
||||||
#if 0
|
|
||||||
init_apic_timer();
|
|
||||||
#endif
|
#endif
|
||||||
|
};
|
||||||
|
if (cpu_init_detected()) {
|
||||||
|
asm("jmp __cpu_reset");
|
||||||
|
}
|
||||||
|
enable_lapic();
|
||||||
|
init_timer();
|
||||||
|
if (!boot_cpu() ) {
|
||||||
|
notify_bsp_ap_is_stopped();
|
||||||
|
stop_this_cpu();
|
||||||
|
}
|
||||||
uart_init();
|
uart_init();
|
||||||
console_init();
|
console_init();
|
||||||
if (boot_cpu() && !cpu_init_detected()) {
|
|
||||||
setup_default_resource_map();
|
setup_default_resource_map();
|
||||||
setup_coherent_ht_domain();
|
setup_coherent_ht_domain();
|
||||||
enumerate_ht_chain();
|
enumerate_ht_chain(0);
|
||||||
// print_pci_devices();
|
distinguish_cpu_resets(0);
|
||||||
enable_smbus();
|
|
||||||
// sdram_initialize();
|
|
||||||
// dump_spd_registers(&cpu0);
|
|
||||||
sdram_initialize(&cpu0);
|
|
||||||
// dump_spd_registers(&cpu1);
|
|
||||||
// sdram_initialize(&cpu1);
|
|
||||||
|
|
||||||
// dump_pci_device(PCI_DEV(0, 0x18, 2));
|
|
||||||
#if 0
|
#if 0
|
||||||
ram_fill( 0x00100000, 0x00180000);
|
print_pci_devices();
|
||||||
ram_verify(0x00100000, 0x00180000);
|
|
||||||
#endif
|
#endif
|
||||||
//#ifdef MEMORY_1024MB
|
enable_smbus();
|
||||||
// ram_fill( 0x00000000, 0x00001000);
|
#if 0
|
||||||
// ram_verify(0x00000000, 0x00001000);
|
dump_spd_registers(&cpu[0]);
|
||||||
//#endif
|
#endif
|
||||||
//#ifdef MEMROY_512MB
|
memreset_setup();
|
||||||
// ram_fill( 0x00000000, 0x01ffffff);
|
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
|
||||||
// ram_verify(0x00000000, 0x01ffffff);
|
|
||||||
//#endif
|
#if 0
|
||||||
/* Check the first 512M */
|
dump_pci_devices();
|
||||||
/* msr_t msr;
|
#endif
|
||||||
|
#if 0
|
||||||
|
dump_pci_device(PCI_DEV(0, 0x18, 2));
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Check all of memory */
|
||||||
|
#if 0
|
||||||
|
msr_t msr;
|
||||||
msr = rdmsr(TOP_MEM);
|
msr = rdmsr(TOP_MEM);
|
||||||
print_debug("TOP_MEM: ");
|
print_debug("TOP_MEM: ");
|
||||||
print_debug_hex32(msr.hi);
|
print_debug_hex32(msr.hi);
|
||||||
print_debug_hex32(msr.lo);
|
print_debug_hex32(msr.lo);
|
||||||
print_debug("\r\n");
|
print_debug("\r\n");
|
||||||
ram_check(0x00000000, msr.lo);
|
#endif
|
||||||
*/
|
|
||||||
/*
|
/*
|
||||||
reg = *((volatile unsigned long *)(APIC_DEFAULT_BASE+APIC_ID));
|
#if 1
|
||||||
print_debug("bootstrap cpu apic_id: ");
|
ram_check(0x00000000, msr.lo);
|
||||||
print_debug_hex32(reg>>24);
|
#else
|
||||||
print_debug("\r\n");
|
#if TOTAL_CPUS < 2
|
||||||
|
// Check 16MB of memory @ 0
|
||||||
|
ram_check(0x00000000, 0x01000000);
|
||||||
|
#else
|
||||||
|
// Check 16MB of memory @ 2GB
|
||||||
|
ram_check(0x80000000, 0x81000000);
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
*/
|
*/
|
||||||
|
|
||||||
// Start AP now
|
|
||||||
reg = pci_read_config32(PCI_DEV(0, 0x19, 0), 0x6C);
|
|
||||||
reg &= 0xffffff8c;
|
|
||||||
reg |= 0x00000070;
|
|
||||||
pci_write_config32(PCI_DEV(0, 0x19, 0), 0x6C, reg); //start AP
|
|
||||||
for(;;) {
|
|
||||||
reg = pci_read_config32(PCI_DEV(0, 0x19, 0), 0x6C);
|
|
||||||
if((reg & (1<<4))==0) break; // wait until AP stop
|
|
||||||
}
|
|
||||||
reg |= 1<<4;
|
|
||||||
pci_write_config32(PCI_DEV(0, 0x19, 0), 0x6C, reg);
|
|
||||||
|
|
||||||
}
|
|
||||||
else {
|
|
||||||
// Need to init second cpu's APIC id
|
|
||||||
// It's AP
|
|
||||||
|
|
||||||
// apic_write(APIC_ID,(1<<24));
|
|
||||||
reg = *((volatile unsigned long *)(APIC_DEFAULT_BASE+APIC_ID));
|
|
||||||
/* print_debug("applicaton cpu apic_id: ");
|
|
||||||
print_debug_hex32(reg>>24);
|
|
||||||
print_debug("\r\n");
|
|
||||||
if((reg>>24)==7){ // FIXME: Need to read NodeID at first.
|
|
||||||
*((volatile unsigned long *)(APIC_DEFAULT_BASE+APIC_ID))=1<<24;
|
|
||||||
}*/
|
|
||||||
if((reg>>24)!=0) {
|
|
||||||
// before hlt clear the ColdResetbit
|
|
||||||
|
|
||||||
//notify BSP that AP is stopped
|
|
||||||
reg = pci_read_config32(PCI_DEV(0, 0x19, 0), 0x6C);
|
|
||||||
reg &= ~(1<<4);
|
|
||||||
pci_write_config32(PCI_DEV(0, 0x19, 0), 0x6C, reg);
|
|
||||||
|
|
||||||
asm("hlt");
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -2,25 +2,37 @@
|
||||||
#include <stdint.h>
|
#include <stdint.h>
|
||||||
#include <device/pci_def.h>
|
#include <device/pci_def.h>
|
||||||
#include <device/pci_ids.h>
|
#include <device/pci_ids.h>
|
||||||
|
#include <arch/io.h>
|
||||||
#include "arch/romcc_io.h"
|
#include "arch/romcc_io.h"
|
||||||
#include "pc80/mc146818rtc_early.c"
|
#include "pc80/mc146818rtc_early.c"
|
||||||
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
|
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
|
||||||
#include "northbridge/amd/amdk8/early_ht.c"
|
#include "northbridge/amd/amdk8/early_ht.c"
|
||||||
|
#include "cpu/p6/boot_cpu.c"
|
||||||
|
#include "northbridge/amd/amdk8/reset_test.c"
|
||||||
|
|
||||||
static void main(void)
|
static void main(void)
|
||||||
{
|
{
|
||||||
if (do_normal_boot()) {
|
|
||||||
/* Nothing special needs to be done to find bus 0 */
|
/* Nothing special needs to be done to find bus 0 */
|
||||||
|
|
||||||
/* Allow the HT devices to be found */
|
/* Allow the HT devices to be found */
|
||||||
enumerate_ht_chain();
|
enumerate_ht_chain(0);
|
||||||
|
|
||||||
/* Setup the 8111 */
|
/* Setup the 8111 */
|
||||||
amd8111_enable_rom();
|
amd8111_enable_rom();
|
||||||
|
|
||||||
/* Jump to the normal image */
|
/* Is this a cpu reset? */
|
||||||
|
if (cpu_init_detected()) {
|
||||||
|
if (last_boot_normal()) {
|
||||||
|
asm("jmp __normal_image");
|
||||||
|
} else {
|
||||||
|
asm("jmp __cpu_reset");
|
||||||
|
}
|
||||||
|
}
|
||||||
|
/* Is this a secondary cpu? */
|
||||||
|
else if (!boot_cpu() && last_boot_normal()) {
|
||||||
|
asm("jmp __normal_image");
|
||||||
|
}
|
||||||
|
/* This is the primary cpu how should I boot? */
|
||||||
|
else if (do_normal_boot()) {
|
||||||
asm("jmp __normal_image");
|
asm("jmp __normal_image");
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -77,6 +77,41 @@ static void disable_probes(void)
|
||||||
print_debug("done.\r\n");
|
print_debug("done.\r\n");
|
||||||
|
|
||||||
}
|
}
|
||||||
|
//BY LYH
|
||||||
|
#define WAIT_TIMES 1000
|
||||||
|
static void wait_ap_stop(u8 node)
|
||||||
|
{
|
||||||
|
unsigned long reg;
|
||||||
|
unsigned long i;
|
||||||
|
for(i=0;i<WAIT_TIMES;i++) {
|
||||||
|
unsigned long regx;
|
||||||
|
regx = pci_read_config32(NODE_HT(node),0x6c);
|
||||||
|
if((regx & (1<<4))==1) break;
|
||||||
|
}
|
||||||
|
reg = pci_read_config32(NODE_HT(node),0x6c);
|
||||||
|
reg &= ~(1<<4); // clear it
|
||||||
|
pci_write_config32(NODE_HT(node), 0x6c, reg);
|
||||||
|
|
||||||
|
}
|
||||||
|
static void notify_bsp_ap_is_stopped(void)
|
||||||
|
{
|
||||||
|
unsigned long reg;
|
||||||
|
unsigned long apic_id;
|
||||||
|
apic_id = *((volatile unsigned long *)(APIC_DEFAULT_BASE+APIC_ID));
|
||||||
|
apic_id >>= 24;
|
||||||
|
/* print_debug("applicaton cpu apic_id: ");
|
||||||
|
print_debug_hex32(apic_id);
|
||||||
|
print_debug("\r\n");
|
||||||
|
}*/
|
||||||
|
if(apic_id!=0) { //AP apic_id == node_id ??
|
||||||
|
// set the ColdResetbit to notify BSP that AP is stopped
|
||||||
|
reg = pci_read_config32(NODE_HT(apic_id), 0x6C);
|
||||||
|
reg |= 1<<4;
|
||||||
|
pci_write_config32(NODE_HT(apic_id), 0x6C, reg);
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
//BY LYH END
|
||||||
|
|
||||||
static void enable_routing(u8 node)
|
static void enable_routing(u8 node)
|
||||||
{
|
{
|
||||||
|
|
@ -111,6 +146,13 @@ static void enable_routing(u8 node)
|
||||||
val=pci_read_config32(NODE_HT(node), 0x6c);
|
val=pci_read_config32(NODE_HT(node), 0x6c);
|
||||||
val &= ~((1<<6)|(1<<5)|(1<<4)|(1<<1)|(1<<0));
|
val &= ~((1<<6)|(1<<5)|(1<<4)|(1<<1)|(1<<0));
|
||||||
pci_write_config32(NODE_HT(node), 0x6c, val);
|
pci_write_config32(NODE_HT(node), 0x6c, val);
|
||||||
|
//BY LYH
|
||||||
|
#if 1
|
||||||
|
if(node!=0) {
|
||||||
|
wait_ap_stop(node);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
//BY LYH END
|
||||||
|
|
||||||
print_debug(" done.\r\n");
|
print_debug(" done.\r\n");
|
||||||
}
|
}
|
||||||
|
|
@ -394,6 +436,42 @@ static unsigned int cpuid(unsigned int op)
|
||||||
|
|
||||||
static void coherent_ht_finalize(unsigned cpus)
|
static void coherent_ht_finalize(unsigned cpus)
|
||||||
{
|
{
|
||||||
|
//BY LYH
|
||||||
|
#if 1
|
||||||
|
static const unsigned int register_values[] = {
|
||||||
|
PCI_ADDR(0, 0x18, 0, 0x84), 0x88ff9c05, 0x11000020,
|
||||||
|
PCI_ADDR(0, 0x18, 0, 0xa4), 0x88ff9c05, 0x11000020,
|
||||||
|
PCI_ADDR(0, 0x18, 0, 0xc4), 0x88ff9c05, 0x770000d0,
|
||||||
|
PCI_ADDR(0, 0x19, 0, 0x84), 0x88ff9c05, 0x770000d0,
|
||||||
|
PCI_ADDR(0, 0x19, 0, 0xa4), 0x88ff9c05, 0x11000020,
|
||||||
|
PCI_ADDR(0, 0x19, 0, 0xc4), 0x88ff9c05, 0x770000d0,
|
||||||
|
|
||||||
|
|
||||||
|
PCI_ADDR(0, 0x18, 0, 0x88), 0xfffff0ff, 0x00000400,
|
||||||
|
PCI_ADDR(0, 0x18, 0, 0xa8), 0xfffff0ff, 0x00000500,
|
||||||
|
PCI_ADDR(0, 0x18, 0, 0xc8), 0xfffff0ff, 0x00000000,
|
||||||
|
PCI_ADDR(0, 0x19, 0, 0x88), 0xfffff0ff, 0x00000000,
|
||||||
|
PCI_ADDR(0, 0x19, 0, 0xa8), 0xfffff0ff, 0x00000500,
|
||||||
|
PCI_ADDR(0, 0x19, 0, 0xc8), 0xfffff0ff, 0x00000000,
|
||||||
|
|
||||||
|
PCI_ADDR(0, 0x18, 0, 0x94), 0xff0000ff, 0x00ff0000,
|
||||||
|
PCI_ADDR(0, 0x18, 0, 0xb4), 0xff0000ff, 0x00000000,
|
||||||
|
PCI_ADDR(0, 0x18, 0, 0xd4), 0xff0000ff, 0x00000000,
|
||||||
|
PCI_ADDR(0, 0x19, 0, 0x94), 0xff0000ff, 0x00000000,
|
||||||
|
PCI_ADDR(0, 0x19, 0, 0xb4), 0xff0000ff, 0x00000000,
|
||||||
|
PCI_ADDR(0, 0x19, 0, 0xd4), 0xff0000ff, 0x00000000,
|
||||||
|
|
||||||
|
};
|
||||||
|
int i;
|
||||||
|
int max;
|
||||||
|
|
||||||
|
|
||||||
|
device_t dev;
|
||||||
|
unsigned where;
|
||||||
|
unsigned long reg;
|
||||||
|
#endif
|
||||||
|
//BY LYH END
|
||||||
|
|
||||||
int node;
|
int node;
|
||||||
bool rev_a0;
|
bool rev_a0;
|
||||||
|
|
||||||
|
|
@ -416,7 +494,7 @@ static void coherent_ht_finalize(unsigned cpus)
|
||||||
pci_write_config32(NODE_HT(node),0x60,val);
|
pci_write_config32(NODE_HT(node),0x60,val);
|
||||||
|
|
||||||
val=pci_read_config32(NODE_HT(node), 0x68);
|
val=pci_read_config32(NODE_HT(node), 0x68);
|
||||||
val |= 0x00008000;
|
val |= 0x0f00c800; // 0x00008000->0f00c800 BY LYH
|
||||||
pci_write_config32(NODE_HT(node),0x68,val);
|
pci_write_config32(NODE_HT(node),0x68,val);
|
||||||
|
|
||||||
if (rev_a0) {
|
if (rev_a0) {
|
||||||
|
|
@ -425,6 +503,28 @@ static void coherent_ht_finalize(unsigned cpus)
|
||||||
pci_write_config32(NODE_HT(node),0xd4,0);
|
pci_write_config32(NODE_HT(node),0xd4,0);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
//BY LYH
|
||||||
|
#if 1
|
||||||
|
print_debug("setting up coherent ht domain....\r\n");
|
||||||
|
max = sizeof(register_values)/sizeof(register_values[0]);
|
||||||
|
for(i = 0; i < max; i += 3) {
|
||||||
|
#if 0
|
||||||
|
print_debug_hex32(i);
|
||||||
|
print_debug(": ");
|
||||||
|
print_debug_hex32(register_values[i]);
|
||||||
|
print_debug(" <-");
|
||||||
|
print_debug_hex32(register_values[i+2]);
|
||||||
|
print_debug("\r\n");
|
||||||
|
#endif
|
||||||
|
dev = register_values[i] & ~0xff;
|
||||||
|
where = register_values[i] & 0xff;
|
||||||
|
reg = pci_read_config32(dev, where);
|
||||||
|
reg &= register_values[i+1];
|
||||||
|
reg |= register_values[i+2];
|
||||||
|
pci_write_config32(dev, where, reg);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
//BY LYH END
|
||||||
|
|
||||||
#if 1
|
#if 1
|
||||||
print_debug("done\r\n");
|
print_debug("done\r\n");
|
||||||
|
|
|
||||||
|
|
@ -1249,7 +1249,14 @@ static void order_dimms(const struct mem_controller *ctrl)
|
||||||
tom |= (1 << (canidate + 24));
|
tom |= (1 << (canidate + 24));
|
||||||
|
|
||||||
/* Recompute the cs base register value */
|
/* Recompute the cs base register value */
|
||||||
|
#if 1 // BY LYH Need to count from 0 for every memory controller
|
||||||
|
csbase = ((tom - (base_k>>15))<< 21) | 1;
|
||||||
|
print_debug("csbase=");
|
||||||
|
print_debug_hex32(csbase);
|
||||||
|
print_debug("\r\n");
|
||||||
|
#else //BY LYH END
|
||||||
csbase = (tom << 21) | 1;
|
csbase = (tom << 21) | 1;
|
||||||
|
#endif
|
||||||
|
|
||||||
/* Increment the top of memory */
|
/* Increment the top of memory */
|
||||||
tom += size;
|
tom += size;
|
||||||
|
|
@ -1276,6 +1283,14 @@ static void order_dimms(const struct mem_controller *ctrl)
|
||||||
print_debug("\r\n");
|
print_debug("\r\n");
|
||||||
#endif
|
#endif
|
||||||
route_dram_accesses(ctrl, base_k, tom_k);
|
route_dram_accesses(ctrl, base_k, tom_k);
|
||||||
|
|
||||||
|
#if 0 //BY LYH
|
||||||
|
if(ctrl->node_id==1) {
|
||||||
|
pci_write_config32(ctrl->f2, DRAM_CSBASE, 0x00000001);
|
||||||
|
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
set_top_mem(tom_k);
|
set_top_mem(tom_k);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -2224,12 +2239,12 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
|
||||||
print_debug_hex32(dcl);
|
print_debug_hex32(dcl);
|
||||||
print_debug("\r\n");
|
print_debug("\r\n");
|
||||||
#endif
|
#endif
|
||||||
#if 1
|
#if 0
|
||||||
dcl &= ~DCL_DimmEccEn;
|
dcl &= ~DCL_DimmEccEn;
|
||||||
#endif
|
#endif
|
||||||
#warning "FIXME set the ECC type to perform"
|
#warning "FIXME set the ECC type to perform"
|
||||||
#warning "FIXME initialize the scrub registers"
|
#warning "FIXME initialize the scrub registers"
|
||||||
#if 0
|
#if 1
|
||||||
if (dcl & DCL_DimmEccEn) {
|
if (dcl & DCL_DimmEccEn) {
|
||||||
print_debug("ECC enabled\r\n");
|
print_debug("ECC enabled\r\n");
|
||||||
}
|
}
|
||||||
|
|
@ -2260,7 +2275,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
|
||||||
} else {
|
} else {
|
||||||
print_debug(" done\r\n");
|
print_debug(" done\r\n");
|
||||||
}
|
}
|
||||||
#if 0
|
#if 1
|
||||||
if (dcl & DCL_DimmEccEn) {
|
if (dcl & DCL_DimmEccEn) {
|
||||||
print_debug("Clearing memory: ");
|
print_debug("Clearing memory: ");
|
||||||
loops = 0;
|
loops = 0;
|
||||||
|
|
|
||||||
|
|
@ -2,3 +2,4 @@ driver amd8111_usb.o
|
||||||
driver amd8111_lpc.o
|
driver amd8111_lpc.o
|
||||||
driver amd8111_ide.o
|
driver amd8111_ide.o
|
||||||
driver amd8111_acpi.o
|
driver amd8111_acpi.o
|
||||||
|
driver amd8111_usb2.o
|
||||||
|
|
|
||||||
|
|
@ -12,7 +12,6 @@ static void pcix_init(device_t dev)
|
||||||
uint16_t word;
|
uint16_t word;
|
||||||
uint8_t byte;
|
uint8_t byte;
|
||||||
|
|
||||||
|
|
||||||
/* Enable memory write and invalidate ??? */
|
/* Enable memory write and invalidate ??? */
|
||||||
byte = pci_read_config8(dev, 0x04);
|
byte = pci_read_config8(dev, 0x04);
|
||||||
byte |= 0x10;
|
byte |= 0x10;
|
||||||
|
|
@ -58,6 +57,14 @@ static void ioapic_enable(device_t dev)
|
||||||
value &= ~((1 << 1) | (1 << 0));
|
value &= ~((1 << 1) | (1 << 0));
|
||||||
}
|
}
|
||||||
pci_write_config32(dev, 0x44, value);
|
pci_write_config32(dev, 0x44, value);
|
||||||
|
|
||||||
|
//BY LYH
|
||||||
|
value = pci_read_config32(dev, 0x4);
|
||||||
|
value |= 6;
|
||||||
|
pci_write_config32(dev, 0x4, value);
|
||||||
|
//BY LYH END
|
||||||
|
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static struct device_operations ioapic_ops = {
|
static struct device_operations ioapic_ops = {
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue