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util/inteltool: add missing L0 and L1 pads for Lewisburg 

The description for L0 and L1 was missed in the datasheet, however,
configuration registers for these pads are present. In addition, the
chipset contains the "GPP_L0/CSME_INTR_IN" and "GPP_L1/CSME_INTR_OUT"
pads in a circuit diagram. Use all available information to add a
description for the missed pads.

Change-Id: I7a0488c26b3df9de1adc037d94ae290837d65dd8
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40044
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Maxim Polyakov 2020-07-16 22:02:43 +03:00 committed by David Hendricks
parent 3c7888bf29
commit ec0551c6b0
1 changed files with 7 additions and 0 deletions
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7
util/inteltool/gpio_names/lewisburg.h
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@ -249,6 +249,13 @@ static const char *const lewisburg_group_k_names[] = {
}; };
static const char *const lewisburg_group_l_names[] = { static const char *const lewisburg_group_l_names[] = {
/*
* The description for L0 and L1 was missed in the datasheet, however, the chipset
* contains the GPP_L0/CSME_INTR_IN and GPP_L1/CSME_INTR_OUT pads in a schematic
* diagram and configuration registers for these pads are present.
*/
"GPP_L0", "CSME_INTR_IN", "n/a", "n/a",
"GPP_L1", "CSME_INTR_OUT", "n/a", "n/a",
"GPP_L2", "TESTCH0_D0", "n/a", "n/a", "GPP_L2", "TESTCH0_D0", "n/a", "n/a",
"GPP_L3", "TESTCH0_D1", "n/a", "n/a", "GPP_L3", "TESTCH0_D1", "n/a", "n/a",
"GPP_L4", "TESTCH0_D2", "n/a", "n/a", "GPP_L4", "TESTCH0_D2", "n/a", "n/a",