Supermicro H8QGI: Fix routing from 16 to 55 in ACPI table

H8QGI board has 2 IO-APICS with 56 IRQ’s:

IOAPIC[0]: GSI  0-23   - SB700 southbridge
IOAPIC[1]: GSI 24-55   - RD890 northbridge

`gDefaultApicDeviceInfoTable[]` structure in northbridge code

    vendorcode/amd/cimx/rd890/nbIoApic.c

has IO-APIC interrupt mapping for HT and IOMMU set to last 31
IRQ pin (24+31=55).

    CONST APIC_DEVICE_INFO gDefaultApicDeviceInfoTable[] = {
    // Group  Swizzling   Port Int Pin
      {0,     0,          31},   //HT
      {0,     0,          31},   //IOMMU
    […]

Also the same value (55) can be found in original Supermicro BIOS ACPI DSDT.

Change-Id: Ie26da1f773716d1b7f5f5f884050ae799afc0b7e
Signed-off-by: Aladyshev Konstantin <aladyshev@nicevt.ru>
Reviewed-on: http://review.coreboot.org/2047
Tested-by: build bot (Jenkins)
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Aladyshev Konstantin 2012-12-18 23:15:55 +04:00 committed by Ronald G. Minnich
parent 7299c139c5
commit ec3daf7e08
1 changed files with 1 additions and 1 deletions

View File

@ -89,7 +89,7 @@ Scope(\_SB) {
Name(APR0, Package(){ Name(APR0, Package(){
/* NB devices in APIC mode */ /* NB devices in APIC mode */
/* Bus 0, Dev 0 - SR5650 HT */ /* Bus 0, Dev 0 - SR5650 HT */
Package() { 0xFFFF, Zero, Zero, 16 }, Package() { 0xFFFF, Zero, Zero, 55 },
/* Bus 0, Dev 1 - CLKCONFIG */ /* Bus 0, Dev 1 - CLKCONFIG */