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aopen/dxplplusu: Move timestamps to common code 

First initialisation is already in cpu/intel/car/romstage.c.

Change-Id: If3e5068b4a9981354f0fca5fc12b6b81de1c8f4b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Kyösti Mälkki 2019-01-09 13:33:39 +02:00
parent 2dce923524
commit ec558682fc
2 changed files with 5 additions and 8 deletions
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8
src/mainboard/aopen/dxplplusu/romstage.c
View File

@ -21,7 +21,6 @@
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/bist.h> #include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h> #include <cpu/intel/romstage.h>
#include <timestamp.h>
#include <southbridge/intel/i82801dx/i82801dx.h> #include <southbridge/intel/i82801dx/i82801dx.h>
#include <northbridge/intel/e7505/raminit.h> #include <northbridge/intel/e7505/raminit.h>
@ -47,9 +46,6 @@ void mainboard_romstage_entry(unsigned long bist)
}, },
}; };
timestamp_init(timestamp_get());
timestamp_add_now(TS_START_ROMSTAGE);
/* Get the serial port running and print a welcome banner */ /* Get the serial port running and print a welcome banner */
lpc47m10x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); lpc47m10x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init(); console_init();
@ -61,15 +57,11 @@ void mainboard_romstage_entry(unsigned long bist)
if (!e7505_mch_is_ready()) { if (!e7505_mch_is_ready()) {
enable_smbus(); enable_smbus();
timestamp_add_now(TS_BEFORE_INITRAM);
/* The real MCH initialisation. */ /* The real MCH initialisation. */
e7505_mch_init(memctrl); e7505_mch_init(memctrl);
/* Hook for post ECC scrub settings and debug. */ /* Hook for post ECC scrub settings and debug. */
e7505_mch_done(memctrl); e7505_mch_done(memctrl);
timestamp_add_now(TS_AFTER_INITRAM);
} }
printk(BIOS_DEBUG, "SDRAM is up.\n"); printk(BIOS_DEBUG, "SDRAM is up.\n");

5
src/northbridge/intel/e7505/raminit.c
View File

@ -37,6 +37,7 @@
#include <assert.h> #include <assert.h>
#include <spd.h> #include <spd.h>
#include <sdram_mode.h> #include <sdram_mode.h>
#include <timestamp.h>
#include "raminit.h" #include "raminit.h"
#include "e7505.h" #include "e7505.h"
@ -1768,6 +1769,8 @@ void e7505_mch_init(const struct mem_controller *memctrl)
RAM_DEBUG_MESSAGE("Northbridge prior to SDRAM init:\n"); RAM_DEBUG_MESSAGE("Northbridge prior to SDRAM init:\n");
DUMPNORTH(); DUMPNORTH();
timestamp_add_now(TS_BEFORE_INITRAM);
sdram_set_registers(memctrl); sdram_set_registers(memctrl);
sdram_set_spd_registers(memctrl); sdram_set_spd_registers(memctrl);
sdram_enable(memctrl); sdram_enable(memctrl);
@ -1777,6 +1780,8 @@ void e7505_mch_done(const struct mem_controller *memctrl)
{ {
sdram_post_ecc(memctrl); sdram_post_ecc(memctrl);
timestamp_add_now(TS_AFTER_INITRAM);
RAM_DEBUG_MESSAGE("Northbridge following SDRAM init:\n"); RAM_DEBUG_MESSAGE("Northbridge following SDRAM init:\n");
DUMPNORTH(); DUMPNORTH();
} }