soc/intel/bsw: Move memory init values into `romstage.h`
`chip.h` is usually used as devicetree interface. Change-Id: Ied30927d68927b86758a84ccf3f5fbd8cce632f1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32592 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -16,7 +16,6 @@
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#include <soc/romstage.h>
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#include <baseboard/variants.h>
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#include <chip.h>
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/* All FSP specific code goes in this block */
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void mainboard_romstage_entry(struct romstage_params *rp)
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@ -17,7 +17,6 @@
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#include <soc/gpio.h>
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#include <soc/pci_devs.h>
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#include <soc/romstage.h>
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#include <chip.h>
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#include "onboard.h"
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#include <boardid.h>
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@ -32,9 +32,6 @@
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#define SVID_CONFIG3 3
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#define SVID_PMIC_CONFIG 8
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#define MEM_DDR3 0
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#define MEM_LPDDR3 1
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enum lpe_clk_src {
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LPE_CLK_SRC_XTAL,
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LPE_CLK_SRC_PLL,
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@ -34,4 +34,8 @@ void set_max_freq(void);
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void program_base_addresses(void);
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int chipset_prev_sleep_state(struct chipset_power_state *ps);
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/* Values for FSP's PcdMemoryTypeEnable */
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#define MEM_DDR3 0
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#define MEM_LPDDR3 1
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#endif /* _SOC_ROMSTAGE_H_ */
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