soc/intel/bsw: Move memory init values into `romstage.h`

`chip.h` is usually used as devicetree interface.

Change-Id: Ied30927d68927b86758a84ccf3f5fbd8cce632f1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32592
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Nico Huber 2019-05-04 17:17:40 +02:00 committed by Patrick Georgi
parent f98f8ebb8c
commit ec562161cd
4 changed files with 4 additions and 5 deletions

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@ -16,7 +16,6 @@
#include <soc/romstage.h>
#include <baseboard/variants.h>
#include <chip.h>
/* All FSP specific code goes in this block */
void mainboard_romstage_entry(struct romstage_params *rp)

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@ -17,7 +17,6 @@
#include <soc/gpio.h>
#include <soc/pci_devs.h>
#include <soc/romstage.h>
#include <chip.h>
#include "onboard.h"
#include <boardid.h>

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@ -32,9 +32,6 @@
#define SVID_CONFIG3 3
#define SVID_PMIC_CONFIG 8
#define MEM_DDR3 0
#define MEM_LPDDR3 1
enum lpe_clk_src {
LPE_CLK_SRC_XTAL,
LPE_CLK_SRC_PLL,

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@ -34,4 +34,8 @@ void set_max_freq(void);
void program_base_addresses(void);
int chipset_prev_sleep_state(struct chipset_power_state *ps);
/* Values for FSP's PcdMemoryTypeEnable */
#define MEM_DDR3 0
#define MEM_LPDDR3 1
#endif /* _SOC_ROMSTAGE_H_ */