mb/google/brya/variants/taeko: Configure GPIOs according to schematics
Update initial gpio configuration for taeko BUG=b:195252436 TEST=FW_NAME=taeko emerge-brya coreboot Change-Id: Ida1edbf874c93f6efac45c276920ead9311ac6f2 Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Joey Peng
Tim Wawrzynczak
parent
c6f241aa09
commit
ecd1bf5785
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@ -0,0 +1,3 @@
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bootblock-y += gpio.c
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ramstage-y += gpio.c
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@ -0,0 +1,181 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <commonlib/helpers.h>
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#include <soc/gpio.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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/* Pad configuration in ramstage */
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static const struct pad_config override_gpio_table[] = {
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/* A6 : ESPI_ALERT1# ==> NC */
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PAD_NC(GPP_A6, NONE),
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/* A7 : SRCCLK_OE7# ==> NC */
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PAD_NC(GPP_A7, NONE),
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/* A8 : SRCCLKREQ7# ==> NC */
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PAD_NC(GPP_A8, NONE),
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/* A12 : SATAXPCIE1 ==> NC */
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PAD_NC(GPP_A12, NONE),
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/* A14 : USB_OC1# ==> NC */
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PAD_NC(GPP_A14, NONE),
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/* A15 : USB_OC2# ==> NC */
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PAD_NC(GPP_A15, NONE),
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/* A18 : DDSP_HPDB ==> NC */
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PAD_NC(GPP_A18, NONE),
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/* A19 : DDSP_HPD1 ==> NC */
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PAD_NC(GPP_A19, NONE),
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/* A20 : DDSP_HPD2 ==> NC */
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PAD_NC(GPP_A20, NONE),
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/* A21 : DDPC_CTRCLK ==> NC */
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PAD_NC(GPP_A21, NONE),
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/* A22 : DDPC_CTRLDATA ==> NC */
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PAD_NC(GPP_A22, NONE),
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/* B2 : VRALERT# ==> NC */
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PAD_NC(GPP_B2, NONE),
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/* B3 : PROC_GP2 ==> NC */
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PAD_NC(GPP_B3, NONE),
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/* B15 : TIME_SYNC0 ==> NC */
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PAD_NC(GPP_B15, NONE),
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/* C3 : SML0CLK ==> NC */
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PAD_NC(GPP_C3, NONE),
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/* C4 : SML0DATA ==> NC */
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PAD_NC(GPP_C4, NONE),
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/* C6 : SML1CLK ==> NC */
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PAD_NC(GPP_C6, NONE),
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/* D3 : ISH_GP3 ==> NC */
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PAD_NC(GPP_D3, NONE),
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/* D5 : SRCCLKREQ0# ==> NC */
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PAD_NC(GPP_D5, NONE),
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/* D9 : ISH_SPI_CS# ==> NC */
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PAD_NC(GPP_D9, NONE),
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/* D10 : ISH_SPI_CLK ==> NC */
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PAD_NC(GPP_D10, NONE),
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/* D13 : ISH_UART0_RXD ==> NC */
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PAD_NC(GPP_D13, NONE),
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/* D14 : ISH_UART0_TXD ==> NC */
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PAD_NC(GPP_D14, NONE),
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/* D15 : ISH_UART0_RTS# ==> NC */
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PAD_NC(GPP_D15, NONE),
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/* D16 : ISH_UART0_CTS# ==> NC */
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PAD_NC(GPP_D16, NONE),
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/* D17 : UART1_RXD ==> NC */
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PAD_NC(GPP_D17, NONE),
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/* E0 : SATAXPCIE0 ==> NC */
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PAD_NC(GPP_E0, NONE),
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/* E4 : SATA_DEVSLP0 ==> NC */
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PAD_NC(GPP_E4, NONE),
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/* E5 : SATA_DEVSLP1 ==> NC */
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PAD_NC(GPP_E5, NONE),
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/* E10 : THC0_SPI1_CS# ==> NC */
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PAD_NC(GPP_E10, NONE),
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/* E16 : RSVD_TP ==> NC */
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PAD_NC(GPP_E16, NONE),
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/* E17 : THC0_SPI1_INT# ==> NC */
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PAD_NC(GPP_E17, NONE),
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/* E18 : DDP1_CTRLCLK ==> NC */
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PAD_NC(GPP_E18, NONE),
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/* E19 : DDP1_CTRLDATA ==> NC */
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PAD_NC(GPP_E19, NONE),
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/* E20 : DDP2_CTRLCLK ==> NC */
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PAD_NC(GPP_E20, NONE),
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/* E21 : DDP2_CTRLDATA ==> NC */
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PAD_NC(GPP_E21, NONE),
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/* F6 : CNV_PA_BLANKING ==> NC */
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PAD_NC(GPP_F6, NONE),
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/* F19 : SRCCLKREQ6# ==> NC */
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PAD_NC(GPP_F19, NONE),
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/* F20 : EXT_PWR_GATE# ==> NC */
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PAD_NC(GPP_F20, NONE),
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/* F21 : EXT_PWR_GATE2# ==> NC */
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PAD_NC(GPP_F21, NONE),
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/* F22 : VNN_CTRL ==> VNN_CTRL */
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PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
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/* F23 : BP105_CTRL ==> PP1050_CTRL */
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PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1),
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/* H8 : I2C4_SDA ==> NC */
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PAD_NC(GPP_H8, NONE),
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/* H9 : I2C4_SCL ==> NC */
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PAD_NC(GPP_H9, NONE),
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/* H13 : I2C7_SCL ==> EN_PP3300_SD */
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PAD_CFG_GPO(GPP_H13, 1, DEEP),
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/* H15 : DDPB_CTRLCLK ==> NC */
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PAD_NC(GPP_H15, NONE),
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/* H17 : DDPB_CTRLDATA ==> NC */
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PAD_NC(GPP_H17, NONE),
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/* H19 : SRCCLKREQ4# ==> NC */
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PAD_NC(GPP_H19, NONE),
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/* H21 : IMGCLKOUT2 ==> NC */
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PAD_NC(GPP_H21, NONE),
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/* H22 : IMGCLKOUT3 ==> NC */
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PAD_NC(GPP_H22, NONE),
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/* H23 : SRCCLKREQ5# ==> NC */
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PAD_NC(GPP_H23, NONE),
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/* R7 : I2S2_RXD ==> NC */
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PAD_NC(GPP_R7, NONE),
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/* S0 : SNDW0_CLK ==> NC */
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PAD_NC(GPP_S0, NONE),
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/* S1 : SNDW0_DATA ==> NC */
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PAD_NC(GPP_S1, NONE),
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/* S4 : SNDW2_CLK ==> NC */
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PAD_NC(GPP_S4, NONE),
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/* S5 : SNDW2_DATA ==> NC */
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PAD_NC(GPP_S5, NONE),
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/* S6 : SNDW3_CLK ==> NC */
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PAD_NC(GPP_S6, NONE),
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/* S7 : SNDW3_DATA ==> NC */
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PAD_NC(GPP_S7, NONE),
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/* GPD11: LANPHYC ==> WWAN_CONFIG1 */
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PAD_NC(GPD11, NONE),
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};
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/* Early pad configuration in bootblock */
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static const struct pad_config early_gpio_table[] = {
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/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
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/* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
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PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
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/* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
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PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
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/*
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* D1 : ISH_GP1 ==> FP_RST_ODL
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* FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
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* To ensure proper power sequencing for the FPMCU device, reset signal is driven low
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* early on in bootblock, followed by enabling of power. Reset signal is deasserted
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* later on in ramstage. Since reset signal is asserted in bootblock, it results in
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* FPMCU not working after a S3 resume. This is a known issue.
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*/
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PAD_CFG_GPO(GPP_D1, 0, DEEP),
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/* D2 : ISH_GP2 ==> EN_FP_PWR */
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PAD_CFG_GPO(GPP_D2, 1, DEEP),
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/* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
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PAD_CFG_GPI(GPP_E13, NONE, DEEP),
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/* E15 : RSVD_TP ==> PCH_WP_OD */
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PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
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/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
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PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
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/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
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PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
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/* H13 : I2C7_SCL ==> EN_PP3300_SD */
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PAD_CFG_GPO(GPP_H13, 1, DEEP),
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};
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const struct pad_config *__weak variant_gpio_override_table(size_t *num)
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{
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*num = ARRAY_SIZE(override_gpio_table);
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return override_gpio_table;
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}
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const struct pad_config *__weak variant_early_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(early_gpio_table);
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return early_gpio_table;
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}
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