src/cpu: Fix typo
Change-Id: I13dec72b2de2a525d45909e697c33fbdc31111cb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
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@ -69,7 +69,7 @@ void intel_model_206ax_finalize_smm(void)
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msr_set_bit(MSR_PP1_POWER_LIMIT, 31);
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#endif
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/* Lock TM interupts - route thermal events to all processors */
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/* Lock TM interrupts - route thermal events to all processors */
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msr_set_bit(MSR_MISC_PWR_MGMT, 22);
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/* Lock memory configuration to protect SMM */
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@ -72,7 +72,7 @@ void intel_cpu_haswell_finalize_smm(void)
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msr_set_bit(MSR_PP1_POWER_LIMIT, 31);
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#endif
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/* Lock TM interupts - route thermal events to all processors */
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/* Lock TM interrupts - route thermal events to all processors */
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msr_set_bit(MSR_MISC_PWR_MGMT, 22);
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/* Lock memory configuration to protect SMM */
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@ -52,6 +52,6 @@ void intel_model_2065x_finalize_smm(void)
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if (cpuid_ecx(1) & (1 << 25))
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msr_set_bit(MSR_FEATURE_CONFIG, 0);
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/* Lock TM interupts - route thermal events to all processors */
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/* Lock TM interrupts - route thermal events to all processors */
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msr_set_bit(MSR_MISC_PWR_MGMT, 22);
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}
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@ -70,7 +70,7 @@ void intel_model_206ax_finalize_smm(void)
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msr_set_bit(MSR_PP1_POWER_LIMIT, 31);
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#endif
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/* Lock TM interupts - route thermal events to all processors */
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/* Lock TM interrupts - route thermal events to all processors */
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msr_set_bit(MSR_MISC_PWR_MGMT, 22);
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/* Lock memory configuration to protect SMM */
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@ -89,7 +89,7 @@ _start16bit:
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* must be loaded at or above 0xffff0000 or below 0x100000.
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*
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* The linker scripts computes gdtptr16_offset by simply returning
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* the low 16 bits. This means that the intial segment used
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* the low 16 bits. This means that the initial segment used
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* when start is called must be 64K aligned. This should not
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* restrict the address as the ip address can be anything.
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*
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@ -17,7 +17,7 @@
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#include <cpu/x86/cr.h>
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#include <cpu/amd/mtrr.h>
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/* The SIPI vector is responsible for initializing the APs in the sytem. It
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/* The SIPI vector is responsible for initializing the APs in the system. It
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* loads microcode, sets up MSRs, and enables caching before calling into
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* C code. */
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