mb/google/volteer: Assert BT_DISABLE_L (GPP_A13) in early_gpio_table
BT_DISABLE_L (GPP_A13) has to asserted in early_gpio_table to reset bluetooth on reset. BUG=b:171085081 TEST=volteer2 boots; scope shows assertion of the signal Change-Id: Iaa5799e9cab69c074b7920604c8a6c85ad07358a Signed-off-by: Alex Levin <levinale@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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@ -400,7 +400,9 @@ static const struct pad_config gpio_table[] = {
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static const struct pad_config early_gpio_table[] = {
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/* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */
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PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
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/* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */
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/* assert reset on reboot */
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PAD_CFG_GPO(GPP_A13, 0, DEEP),
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/* A17 : DDSP_HPDC ==> MEM_CH_SEL */
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PAD_CFG_GPI(GPP_A17, NONE, DEEP),
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@ -127,6 +127,9 @@ static const struct pad_config override_gpio_table[] = {
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static const struct pad_config early_gpio_table[] = {
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/* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */
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PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
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/* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */
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/* assert reset on reboot */
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PAD_CFG_GPO(GPP_A13, 0, DEEP),
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/* A17 : DDSP_HPDC ==> MEM_CH_SEL */
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PAD_CFG_GPI(GPP_A17, NONE, DEEP),
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@ -166,6 +166,9 @@ static const struct pad_config override_gpio_table[] = {
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static const struct pad_config early_gpio_table[] = {
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/* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */
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PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
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/* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */
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/* assert reset on reboot */
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PAD_CFG_GPO(GPP_A13, 0, DEEP),
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/* A17 : DDSP_HPDC ==> MEM_CH_SEL */
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PAD_CFG_GPI(GPP_A17, NONE, DEEP),
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@ -180,6 +180,9 @@ static const struct pad_config override_gpio_table[] = {
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static const struct pad_config early_gpio_table[] = {
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/* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */
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PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
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/* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */
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/* assert reset on reboot */
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PAD_CFG_GPO(GPP_A13, 0, DEEP),
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/* A17 : DDSP_HPDC ==> MEM_CH_SEL */
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PAD_CFG_GPI(GPP_A17, NONE, DEEP),
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/* B2 : VRALERT# ==> EN_PP3300_SSD */
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@ -198,7 +198,9 @@ const struct pad_config *variant_override_gpio_table(size_t *num)
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static const struct pad_config early_gpio_table[] = {
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/* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */
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PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
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/* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */
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/* assert reset on reboot */
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PAD_CFG_GPO(GPP_A13, 0, DEEP),
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/* A17 : DDSP_HPDC ==> MEM_CH_SEL */
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PAD_CFG_GPI(GPP_A17, NONE, DEEP),
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@ -109,6 +109,9 @@ static const struct pad_config override_gpio_table[] = {
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static const struct pad_config early_gpio_table[] = {
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/* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */
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PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
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/* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */
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/* assert reset on reboot */
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PAD_CFG_GPO(GPP_A13, 0, DEEP),
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/* A17 : DDSP_HPDC ==> MEM_CH_SEL */
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PAD_CFG_GPI(GPP_A17, NONE, DEEP),
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/* A22 : DDPC_CTRLDATA ==> EN_PP3300_SSD */
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@ -155,7 +155,9 @@ static const struct pad_config gpio_table[] = {
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static const struct pad_config early_gpio_table[] = {
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/* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */
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PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
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/* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */
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/* assert reset on reboot */
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PAD_CFG_GPO(GPP_A13, 0, DEEP),
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/* A17 : DDSP_HPDC ==> MEM_CH_SEL */
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PAD_CFG_GPI(GPP_A17, NONE, DEEP),
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@ -189,6 +189,9 @@ const struct pad_config *variant_override_gpio_table(size_t *num)
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static const struct pad_config early_gpio_table[] = {
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/* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */
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PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
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/* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */
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/* assert reset on reboot */
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PAD_CFG_GPO(GPP_A13, 0, DEEP),
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/* A17 : DDSP_HPDC ==> MEM_CH_SEL */
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PAD_CFG_GPI(GPP_A17, NONE, DEEP),
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@ -197,6 +197,9 @@ const struct pad_config *variant_override_gpio_table(size_t *num)
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static const struct pad_config early_gpio_table[] = {
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/* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */
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PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
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/* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */
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/* assert reset on reboot */
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PAD_CFG_GPO(GPP_A13, 0, DEEP),
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/* A17 : DDSP_HPDC ==> MEM_CH_SEL */
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PAD_CFG_GPI(GPP_A17, NONE, DEEP),
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@ -187,6 +187,9 @@ const struct pad_config *variant_override_gpio_table(size_t *num)
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static const struct pad_config early_gpio_table[] = {
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/* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */
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PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
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/* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */
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/* assert reset on reboot */
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PAD_CFG_GPO(GPP_A13, 0, DEEP),
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/* A17 : DDSP_HPDC ==> MEM_CH_SEL */
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PAD_CFG_GPI(GPP_A17, NONE, DEEP),
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@ -210,6 +210,9 @@ static const struct pad_config override_gpio_table[] = {
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static const struct pad_config early_gpio_table[] = {
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/* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */
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PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
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/* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */
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/* assert reset on reboot */
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PAD_CFG_GPO(GPP_A13, 0, DEEP),
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/* A17 : DDSP_HPDC ==> MEM_CH_SEL */
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PAD_CFG_GPI(GPP_A17, NONE, DEEP),
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@ -212,6 +212,9 @@ static const struct pad_config override_gpio_table[] = {
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static const struct pad_config early_gpio_table[] = {
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/* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */
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PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
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/* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */
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/* assert reset on reboot */
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PAD_CFG_GPO(GPP_A13, 0, DEEP),
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/* A17 : DDSP_HPDC ==> MEM_CH_SEL */
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PAD_CFG_GPI(GPP_A17, NONE, DEEP),
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@ -239,6 +239,9 @@ const struct pad_config *variant_override_gpio_table(size_t *num)
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static const struct pad_config early_gpio_table[] = {
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/* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */
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PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
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/* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */
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/* assert reset on reboot */
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PAD_CFG_GPO(GPP_A13, 0, DEEP),
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/* A17 : DDSP_HPDC ==> MEM_CH_SEL */
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PAD_CFG_GPI(GPP_A17, NONE, DEEP),
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