soc/amd/*/psp: move MSR_CU_CBBCFG to common and rename to MSR_PSP_ADDR
TEST=Checked that the MSR is the same for Stoneyridge, Picasso and Cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id15715ed1c17f4fc475985dcb1c31a83713ee65c Reviewed-on: https://review.coreboot.org/c/coreboot/+/50149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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@ -3,6 +3,8 @@
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#ifndef AMD_BLOCK_PSP_H
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#define AMD_BLOCK_PSP_H
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#define MSR_PSP_ADDR 0xc00110a2
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/* Get the mailbox base address - specific to family of device. */
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void *soc_get_mbox_address(void);
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@ -8,15 +8,14 @@
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#include <amdblocks/smi.h>
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#define PSP_MAILBOX_OFFSET 0x10570
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#define MSR_CU_CBBCFG 0xc00110a2
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void *soc_get_mbox_address(void)
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{
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uintptr_t psp_mmio;
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psp_mmio = rdmsr(MSR_CU_CBBCFG).lo;
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psp_mmio = rdmsr(MSR_PSP_ADDR).lo;
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if (psp_mmio == 0xffffffff) {
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printk(BIOS_WARNING, "PSP: MSR_CU_CBBCFG uninitialized\n");
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printk(BIOS_WARNING, "PSP: MSR_PSP_ADDR uninitialized\n");
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return 0;
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}
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@ -205,8 +205,6 @@ void soc_enable_psp_early(void);
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#define BAR3HIDE BIT(12) /* Bit to hide BAR3 addr */
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#define PSP_MAILBOX_BAR_EN BIT(4)
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#define MSR_CU_CBBCFG 0xc00110a2 /* PSP Pvt Blk Base Addr */
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typedef struct aoac_devs {
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unsigned int :5;
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unsigned int ic0e:1; /* 5: I2C0 */
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@ -44,9 +44,9 @@ void *soc_get_mbox_address(void)
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/* Determine if Bar3Hide has been set, and if hidden get the base from
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* the MSR instead. */
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if (pci_read_config32(SOC_PSP_DEV, PSP_BAR_ENABLES) & BAR3HIDE) {
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psp_mmio = rdmsr(MSR_CU_CBBCFG).lo;
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psp_mmio = rdmsr(MSR_PSP_ADDR).lo;
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if (psp_mmio == 0xffffffff) {
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printk(BIOS_WARNING, "PSP: BAR hidden, MSR val uninitialized\n");
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printk(BIOS_WARNING, "PSP: BAR hidden, MSR_PSP_ADDR uninitialized\n");
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return 0;
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}
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} else {
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