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mb/google/kahlee: Drop macro H1_PCH_INT 

This change drops H1_PCH_INT macro for GPIO_9 since it is the same
across all variants. Also, the name differed from the schematics
version `H1_PCH_INT_ODL` creating confusion.

Change-Id: I7b038426a984d8abc460a0da3ee1dc5559d7ad5f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Furquan Shaikh 2020-07-02 13:47:43 -07:00
parent aff9f54e6b
commit ee68b88bab
2 changed files with 1 additions and 4 deletions
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3
src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h
View File

@ -11,9 +11,6 @@
# define MEM_CONFIG2 GPIO_131 # define MEM_CONFIG2 GPIO_131
# define MEM_CONFIG3 GPIO_132 # define MEM_CONFIG3 GPIO_132
/* CR50 interrupt pin */
#define H1_PCH_INT GPIO_9
/* SPI Write protect */ /* SPI Write protect */
#define CROS_WP_GPIO GPIO_122 #define CROS_WP_GPIO GPIO_122
#define GPIO_EC_IN_RW GPIO_15 #define GPIO_EC_IN_RW GPIO_15

2
src/mainboard/google/kahlee/variants/baseboard/tpm_tis.c
View File

@ -6,5 +6,5 @@
int tis_plat_irq_status(void) int tis_plat_irq_status(void)
{ {
return gpio_interrupt_status(H1_PCH_INT); return gpio_interrupt_status(GPIO_9);
} }