Skylake: Add ASL code to enable GPIO controller
This patch enables GPIO controller for skylake. It adds community base addresses and offset for Community0, Community1, and Community3. Community2 is not exposed in BIOS or enabled in the kernel driver. Also, clean up the carry over GWAK implementation from BDW. BRANCH=None BUG=chrome-os-partner:42393 TEST=cat /sys/kernel/debug/gpio should list of GPIOs TEST=export a GPIO pin using /sys/class/gpio/export Original-Change-Id: I891c40589d3dbd796cf593626472c7b5674a1ae0 Original-Signed-off-by: Archana Patni <archana.patni@intel.com> Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/291230 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Change-Id: I7481ce682ccae872fddf81b3188c3415d5d3f7d9 Signed-off-by: Archana Patni <archana.patni@intel.com> Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Reviewed-on: http://review.coreboot.org/11191 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Archana Patni
Aaron Durbin
parent
39bdb0bbcf
commit
ee9662824d
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@ -18,46 +18,64 @@
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* Foundation, Inc.
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* Foundation, Inc.
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*/
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*/
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#include <soc/irq.h>
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#include <soc/iomap.h>
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#include <soc/pcr.h>
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#include <soc/gpio_defs.h>
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/* PCR Register Access Methods PCR Dword Read arg0: PID arg1: Offset */
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Method (PCRR, 2, Serialized)
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{
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Add (ShiftLeft (Arg0, PCR_PORTID_SHIFT), Arg1, Local0)
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Add (PCH_PCR_BASE_ADDRESS, Local0, Local0)
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OperationRegion (PCR0, SystemMemory, Local0, 0x4)
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Field(PCR0, DWordAcc, Lock, Preserve)
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{
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Offset(0x00),
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DAT0, 32
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}
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Return (DAT0)
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}
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Device (GPIO)
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Device (GPIO)
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{
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{
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// GPIO Controller
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/* GPIO Controller */
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Method (_HID)
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Name (_HID, "INT344B")
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{
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//Sunrisepoint-LP PCH
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Return ("INT344B")
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}
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Name (_UID, 1)
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Name (_UID, 1)
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Name (RBUF, ResourceTemplate()
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Name (RBUF, ResourceTemplate()
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{
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{
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DWordIo (ResourceProducer,
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Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, _R0)
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MinFixed, // IsMinFixed
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Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, _R1)
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MaxFixed, // IsMaxFixed
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Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, _R3)
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PosDecode, // Decode
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Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, _R4)
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EntireRange, // ISARanges
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{
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0x00000000, // AddressGranularity
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GPIO_IRQ14,
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0x00000000, // AddressMinimum
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}
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0x00000000, // AddressMaximum
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0x00000000, // AddressTranslation
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0x00000000, // RangeLength
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, // ResourceSourceIndex
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, // ResourceSource
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BAR0)
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// Disabled due to IRQ storm: http://crosbug.com/p/29548
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//Interrupt (ResourceConsumer,
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// Level, ActiveHigh, Shared, , , ) {14}
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})
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})
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Method (_CRS, 0, NotSerialized)
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Method (_CRS, 0, NotSerialized) /* _CRS: Current Resource Settings */
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{
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{
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CreateDwordField (^RBUF, ^BAR0._MIN, BMIN)
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CreateDWordField (^RBUF, ^_R0._BAS, COM0)
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CreateDwordField (^RBUF, ^BAR0._MAX, BMAX)
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CreateDWordField (^RBUF, ^_R1._BAS, COM1)
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CreateDwordField (^RBUF, ^BAR0._LEN, BLEN)
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CreateDWordField (^RBUF, ^_R3._BAS, COM3)
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CreateDWordField (^RBUF, ^_R4._INT, IRQN)
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Store (GPIO_BASE_SIZE, BLEN)
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Store (Add (PCH_PCR_BASE_ADDRESS,
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Store (GPIO_BASE_ADDRESS, BMIN)
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ShiftLeft (PID_GPIOCOM0, PCR_PORTID_SHIFT)), COM0)
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Store (Subtract (Add (GPIO_BASE_ADDRESS,
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Store (Add (PCH_PCR_BASE_ADDRESS,
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GPIO_BASE_SIZE), 1), BMAX)
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ShiftLeft (PID_GPIOCOM1, PCR_PORTID_SHIFT)), COM1)
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Store (Add (PCH_PCR_BASE_ADDRESS,
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ShiftLeft (PID_GPIOCOM3, PCR_PORTID_SHIFT)), COM3)
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Store (And (PCRR (PID_GPIOCOM0, MISCCFG_OFFSET),
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GPIO_DRIVER_IRQ_ROUTE_MASK), Local0)
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If (LEqual (Local0, GPIO_DRIVER_IRQ_ROUTE_IRQ14)) {
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Store (GPIO_IRQ14, IRQN)
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} Else {
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Store (GPIO_IRQ15, IRQN)
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}
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Return (RBUF)
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Return (RBUF)
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}
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}
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@ -66,73 +84,4 @@ Device (GPIO)
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{
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{
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Return (0xF)
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Return (0xF)
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}
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}
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// GWAK: Setup GPIO as ACPI GPE for Wake
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// Arg0: GPIO Number
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Method (GWAK, 1, NotSerialized)
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{
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// Local0 = GPIO Base Address
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Store (And (GPBS, Not(0x1)), Local0)
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// Local1 = BANK, Local2 = OFFSET
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Divide (Arg0, 32, Local2, Local1)
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//
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// Set OWNER to ACPI
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//
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// Local3 = GPIOBASE + GPIO_OWN(BANK)
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Store (Add (Local0, Multiply (Local1, 0x4)), Local3)
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// GPIO_OWN(BANK)
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OperationRegion (IOWN, SystemIO, Local3, 4)
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Field (IOWN, AnyAcc, NoLock, Preserve) {
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GOWN, 32,
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}
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// GPIO_OWN[GPIO] = 0 (ACPI)
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Store (And (GOWN, Not (ShiftLeft (0x1, Local2))), GOWN)
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//
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// Set ROUTE to SCI
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//
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// Local3 = GPIOBASE + GPIO_ROUTE(BANK)
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Store (Add (Add (Local0, 0x30), Multiply (Local1, 0x4)), Local3)
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// GPIO_ROUTE(BANK)
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OperationRegion (IROU, SystemIO, Local3, 4)
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Field (IROU, AnyAcc, NoLock, Preserve) {
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GROU, 32,
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}
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// GPIO_ROUTE[GPIO] = 0 (SCI)
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Store (And (GROU, Not (ShiftLeft (0x1, Local2))), GROU)
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//
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// Set GPnCONFIG to GPIO|INPUT|INVERT
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//
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// Local3 = GPIOBASE + GPnCONFIG0(GPIO)
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Store (Add (Add (Local0, 0x100), Multiply (Arg0, 0x8)), Local3)
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// GPnCONFIG(GPIO)
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OperationRegion (GPNC, SystemIO, Local3, 8)
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Field (GPNC, AnyAcc, NoLock, Preserve) {
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GMOD, 1, // MODE: 0=NATIVE 1=GPIO
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, 1,
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GIOS, 1, // IO_SEL: 0=OUTPUT 1=INPUT
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GINV, 1, // INVERT: 0=NORMAL 1=INVERT
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GLES, 1, // LxEB: 0=EDGE 1=LEVEL
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, 24,
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ILVL, 1, // INPUT: 0=LOW 1=HIGH
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OLVL, 1, // OUTPUT: 0=LOW 1=HIGH
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GPWP, 2, // PULLUP: 00=NONE 01=DOWN 10=UP 11=INVALID
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ISEN, 1, // SENSE: 0=ENABLE 1=DISABLE
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}
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Store (0x1, GMOD) // GPIO
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Store (0x1, GIOS) // INPUT
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Store (0x1, GINV) // INVERT
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}
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}
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}
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@ -476,4 +476,9 @@
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#define PAD_TERM_667_PU 13
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#define PAD_TERM_667_PU 13
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#define PAD_TERM_NATIVE 15
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#define PAD_TERM_NATIVE 15
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#define MISCCFG_OFFSET 0x10
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#define GPIO_DRIVER_IRQ_ROUTE_MASK 8
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#define GPIO_DRIVER_IRQ_ROUTE_IRQ14 0
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#define GPIO_DRIVER_IRQ_ROUTE_IRQ15 8
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#endif /* _SOC_GPIO_DEFS_H_ */
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#endif /* _SOC_GPIO_DEFS_H_ */
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@ -57,6 +57,8 @@
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#define PCH_PWRM_BASE_ADDRESS 0xfe000000
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#define PCH_PWRM_BASE_ADDRESS 0xfe000000
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#define PCH_PWRM_BASE_SIZE 0x10000
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#define PCH_PWRM_BASE_SIZE 0x10000
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#define GPIO_BASE_SIZE 0x10000
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/*
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/*
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* I/O port address space
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* I/O port address space
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*/
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*/
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@ -66,10 +68,6 @@
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#define ACPI_BASE_ADDRESS 0x1800
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#define ACPI_BASE_ADDRESS 0x1800
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#define ACPI_BASE_SIZE 0x100
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#define ACPI_BASE_SIZE 0x100
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/* FIXME: not applicable as there is no I/O space for gpio access. */
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#define GPIO_BASE_ADDRESS 0x1400
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#define GPIO_BASE_SIZE 0x400
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#define TCO_BASE_ADDDRESS 0x400
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#define TCO_BASE_ADDDRESS 0x400
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#define TCO_BASE_SIZE 0x20
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#define TCO_BASE_SIZE 0x20
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@ -17,6 +17,8 @@
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#ifndef _SOC_IRQ_H_
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#ifndef _SOC_IRQ_H_
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#define _SOC_IRQ_H_
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#define _SOC_IRQ_H_
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#define GPIO_IRQ14 14
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#define GPIO_IRQ15 15
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#define LPSS_I2C0_IRQ 16
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#define LPSS_I2C0_IRQ 16
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#define LPSS_I2C1_IRQ 17
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#define LPSS_I2C1_IRQ 17
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#define LPSS_I2C2_IRQ 18
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#define LPSS_I2C2_IRQ 18
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