mb/google/nissa/var/uldren: Update DPTF parameters and tcc_offset

Follow the Project_Uldren_Thermal_paramters_list_2023_0626.xlsx to
modify DPTF parameters and tcc_offset.
- Set tcc_offset to 3.
- Update Critical Policy trip point.
- Update Power Limits PL1 minimum step size to control limits (in mW).

BUG=b:282598257
BRANCH=firmware-nissa-15217.B
TEST=boot uldren to ChromeOS and pass thermal test.

Change-Id: Ic5bbb3aa3b036a1eae8a95f63b570db2dc6da978
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76105
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Yang <paul.f.yang@intel.corp-partner.google.com>
Reviewed-by: Ivan Chen <yulunchen@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
This commit is contained in:
Dtrain Hsu 2023-06-27 10:50:51 +08:00 committed by Eric Lai
parent 5c10eaf8c2
commit eebf63c0c3

View file

@ -106,6 +106,8 @@ chip soc/intel/alderlake
.vnn_icc_max_ma = 500,
}"
register "tcc_offset" = "3"
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
@ -175,10 +177,10 @@ chip soc/intel/alderlake
}"
## Critical Policy
register "policies.critical" = "{
[0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 98, SHUTDOWN),
[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 98, SHUTDOWN),
[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 98, SHUTDOWN),
[0] = DPTF_CRITICAL(CPU, 130, SHUTDOWN),
[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 105, SHUTDOWN),
[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 105, SHUTDOWN),
[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 105, SHUTDOWN),
}"
register "controls.power_limits" = "{
@ -187,7 +189,7 @@ chip soc/intel/alderlake
.max_power = 6000,
.time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 28 * MSECS_PER_SEC,
.granularity = 250
.granularity = 125
},
.pl2 = {
.min_power = 25000,