amd/stoneyridge: Move pm/smi_read/write functions to util file

Pull all pm_read and write, smi_read and write variants into a single
file.

Change-Id: I87d17361f923a60c95ab66e150445a6a0431b772
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>

src/soc/amd/stoneyridge/Makefile.inc

@@ -74,6 +74,7 @@ ramstage-y += fixme.c
 ramstage-y += gpio.c
 ramstage-y += hda.c
 ramstage-y += southbridge.c
+ramstage-y += sb_util.c
 ramstage-$(CONFIG_STONEYRIDGE_IMC_FWM) += imc.c
 ramstage-y += lpc.c
 ramstage-y += model_15_init.c
@@ -92,6 +93,7 @@ ramstage-y += tsc_freq.c
 
 smm-y += smihandler.c
 smm-y += smi_util.c
+smm-y += sb_util.c
 smm-y += tsc_freq.c
 smm-$(CONFIG_DEBUG_SMI) += uart.c
 

src/soc/amd/stoneyridge/include/soc/smi.h

@@ -20,9 +20,6 @@
 
 #include <arch/io.h>
 
-/* ACPI_MMIO_BASE + 0x200 -- leave this string here so grep catches it. */
-#define SMI_BASE			0xfed80200
-
 #define SMI_SCI_STATUS			0x10
 
 /* SMI source and status */
@@ -197,26 +194,6 @@ enum smi_lvl {
 	SMI_LVL_HIGH = 1,
 };
 
-static inline uint32_t smi_read32(uint8_t offset)
-{
-	return read32((void *)(SMI_BASE + offset));
-}
-
-static inline void smi_write32(uint8_t offset, uint32_t value)
-{
-	write32((void *)(SMI_BASE + offset), value);
-}
-
-static inline uint16_t smi_read16(uint8_t offset)
-{
-	return read16((void *)(SMI_BASE + offset));
-}
-
-static inline void smi_write16(uint8_t offset, uint16_t value)
-{
-	write16((void *)(SMI_BASE + offset), value);
-}
-
 void configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level);
 void disable_gevent_smi(uint8_t gevent);
 void enable_acpi_cmd_smi(void);

src/soc/amd/stoneyridge/include/soc/southbridge.h

@@ -25,10 +25,9 @@
 
 #define IO_APIC2_ADDR			0xfec20000
 
-/* Offsets from ACPI_MMIO_BASE
- * This is defined by AGESA, but we don't include AGESA headers to avoid
- * polluting the namespace.
- */
+/* Offsets from ACPI_MMIO_BASE */
+#define APU_SMI_BASE			0xfed80200
+
 #define PM_MMIO_BASE			0xfed80300
 
 #define APU_UART0_BASE			0xfedc6000
@@ -194,6 +193,10 @@ u32 pm_read32(u8 reg);
 void pm_write8(u8 reg, u8 value);
 void pm_write16(u8 reg, u16 value);
 void pm_write32(u8 reg, u32 value);
+u16 smi_read16(u8 reg);
+u32 smi_read32(u8 reg);
+void smi_write16(u8 reg, u16 value);
+void smi_write32(u8 reg, u32 value);
 int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
 void s3_resume_init_data(void *FchParams);
 int s3_save_nvram_early(u32 dword, int size, int  nvram_pos);

src/soc/amd/stoneyridge/sb_util.c

@@ -0,0 +1,66 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/southbridge.h>
+
+void pm_write8(u8 reg, u8 value)
+{
+	write8((void *)(PM_MMIO_BASE + reg), value);
+}
+
+u8 pm_read8(u8 reg)
+{
+	return read8((void *)(PM_MMIO_BASE + reg));
+}
+
+void pm_write16(u8 reg, u16 value)
+{
+	write16((void *)(PM_MMIO_BASE + reg), value);
+}
+
+u16 pm_read16(u8 reg)
+{
+	return read16((void *)(PM_MMIO_BASE + reg));
+}
+
+void pm_write32(u8 reg, u32 value)
+{
+	write32((void *)(PM_MMIO_BASE + reg), value);
+}
+
+u32 pm_read32(u8 reg)
+{
+	return read32((void *)(PM_MMIO_BASE + reg));
+}
+
+void smi_write32(uint8_t offset, uint32_t value)
+{
+	write32((void *)(APU_SMI_BASE + offset), value);
+}
+
+uint32_t smi_read32(uint8_t offset)
+{
+	return read32((void *)(APU_SMI_BASE + offset));
+}
+
+uint16_t smi_read16(uint8_t offset)
+{
+	return read16((void *)(APU_SMI_BASE + offset));
+}
+
+void smi_write16(uint8_t offset, uint16_t value)
+{
+	write16((void *)(APU_SMI_BASE + offset), value);
+}

src/soc/amd/stoneyridge/smi.c

@@ -9,6 +9,7 @@
 
 #include <console/console.h>
 #include <cpu/cpu.h>
+#include <soc/southbridge.h>
 #include <soc/smi.h>
 
 void smm_setup_structures(void *gnvs, void *tcg, void *smi1)

src/soc/amd/stoneyridge/smi_util.c

@@ -6,6 +6,7 @@
  */
 
 #include <console/console.h>
+#include <soc/southbridge.h>
 #include <soc/smi.h>
 
 static void configure_smi(uint8_t smi_num, uint8_t mode)

src/soc/amd/stoneyridge/southbridge.c

@@ -38,36 +38,6 @@ int acpi_get_sleep_type(void)
 	return (int)tmp;
 }
 
-void pm_write8(u8 reg, u8 value)
-{
-	write8((void *)(PM_MMIO_BASE + reg), value);
-}
-
-u8 pm_read8(u8 reg)
-{
-	return read8((void *)(PM_MMIO_BASE + reg));
-}
-
-void pm_write16(u8 reg, u16 value)
-{
-	write16((void *)(PM_MMIO_BASE + reg), value);
-}
-
-u16 pm_read16(u8 reg)
-{
-	return read16((void *)(PM_MMIO_BASE + reg));
-}
-
-void pm_write32(u8 reg, u32 value)
-{
-	write32((void *)(PM_MMIO_BASE + reg), value);
-}
-
-u32 pm_read32(u8 reg)
-{
-	return read32((void *)(PM_MMIO_BASE + reg));
-}
-
 void sb_enable(device_t dev)
 {
 	printk(BIOS_DEBUG, "%s\n", __func__);