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cpu/intel/car/*/cache_as_ram.S: Add brackets around operand 

Change-Id: I644c38c9b8383db25a970dc7a5ec8765980298ed
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/31291
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans 2019-02-08 16:27:35 +01:00 committed by Kyösti Mälkki
parent 8da24f156f
commit eeedf83bcd
2 changed files with 2 additions and 2 deletions
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2
src/cpu/intel/car/non-evict/cache_as_ram.S
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@ -118,7 +118,7 @@ addrsize_set_high:
/* Enable cache for our code in Flash because we do XIP here */ /* Enable cache for our code in Flash because we do XIP here */
movl $MTRR_PHYS_BASE(1), %ecx movl $MTRR_PHYS_BASE(1), %ecx
xorl %edx, %edx xorl %edx, %edx
movl $CACHE_ROM_BASE | MTRR_TYPE_WRPROT, %eax movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax
wrmsr wrmsr
movl $MTRR_PHYS_MASK(1), %ecx movl $MTRR_PHYS_MASK(1), %ecx

2
src/cpu/intel/car/p4-netburst/cache_as_ram.S
View File

@ -304,7 +304,7 @@ no_msr_11e:
/* Cache the whole rom to fetch microcode updates */ /* Cache the whole rom to fetch microcode updates */
movl $MTRR_PHYS_BASE(1), %ecx movl $MTRR_PHYS_BASE(1), %ecx
xorl %edx, %edx xorl %edx, %edx
movl $CACHE_ROM_BASE | MTRR_TYPE_WRPROT, %eax movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax
wrmsr wrmsr
movl $MTRR_PHYS_MASK(1), %ecx movl $MTRR_PHYS_MASK(1), %ecx