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nb/intel/{gm45,i945,pineview}: Use macro instead of GGC address 

Change-Id: I233e835180fd445961b6deb74ea7afc2821c236e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Elyes HAOUAS 2018-10-04 13:50:14 +02:00 committed by Patrick Georgi
parent 6f027ff28a
commit ef20ecc92b
3 changed files with 3 additions and 3 deletions
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2
src/northbridge/intel/gm45/iommu.c
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@ -46,7 +46,7 @@ void init_iommu()
MCHBAR32(0x20) = IOMMU_BASE4 | 1; /* all other DMA sources */
/* clear GTT */
u32 gtt = pci_read_config16(PCI_DEV(0, 0, 0), 0x52);
u16 gtt = pci_read_config16(PCI_DEV(0, 0, 0), D0F0_GGC);
if (gtt & 0x400) { /* VT mode */
pci_devfn_t igd = PCI_DEV(0, 2, 0);

2
src/northbridge/intel/i945/early_init.c
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@ -685,7 +685,7 @@ static void i945_setup_pci_express_x16(void)
if (reg32 == 0x030000) {
printk(BIOS_DEBUG, "PCIe device is VGA. Disabling IGD.\n");
reg16 = (1 << 1);
pci_write_config16(PCI_DEV(0, 0x0, 0), 0x52, reg16);
pci_write_config16(PCI_DEV(0, 0x0, 0), GGC, reg16);
reg32 = pci_read_config32(PCI_DEV(0, 0x0, 0), DEVEN);
reg32 &= ~(DEVEN_D2F0 | DEVEN_D2F1);

2
src/northbridge/intel/pineview/gma.c
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@ -98,7 +98,7 @@ static void intel_gma_init(const struct northbridge_intel_pineview_config *info,
gtt_setup(mmio);
pci_write_config16(vga, 0x52, 0x130);
pci_write_config16(vga, GGC, 0x130);
/* Disable VGA. */
write32(mmio + VGACNTRL, VGA_DISP_DISABLE);