Remove VIA C7 CPU support
Change-Id: Ib8c943e01ac293bdbf37f43ff72dbb636b46a8af Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26681 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Kyösti Mälkki
parent
5ceaf7bf5f
commit
ef3f94a5db
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@ -1,2 +1 @@
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subdirs-$(CONFIG_CPU_VIA_C7) += c7
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subdirs-$(CONFIG_CPU_VIA_NANO) += nano
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@ -1,26 +0,0 @@
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config CPU_VIA_C7
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bool
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if CPU_VIA_C7
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config CPU_SPECIFIC_OPTIONS
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def_bool y
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select ARCH_BOOTBLOCK_X86_32
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select ARCH_VERSTAGE_X86_32
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select ARCH_ROMSTAGE_X86_32
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select ARCH_RAMSTAGE_X86_32
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# Missing tsc_freq_mhz and TSC_CONSTANT_RATE
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#select UDELAY_TSC
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select UDELAY_IO
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select MMX
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select SSE2
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config DCACHE_RAM_BASE
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hex
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default 0xffef0000
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config DCACHE_RAM_SIZE
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hex
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default 0x8000
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endif # CPU_VIA_C7
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@ -1,10 +0,0 @@
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subdirs-y += ../../x86/tsc
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subdirs-y += ../../x86/mtrr
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subdirs-y += ../../x86/lapic
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subdirs-y += ../../x86/cache
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subdirs-y += ../../x86/smm
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subdirs-y += ../../intel/microcode
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ramstage-y += c7_init.c
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cpu_incs-y += $(src)/cpu/via/car/cache_as_ram.inc
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@ -1,226 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* (C) 2007-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <device/device.h>
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#include <console/console.h>
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#include <delay.h>
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#include <stdlib.h>
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#include <cpu/cpu.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/lapic.h>
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#include <cpu/x86/cache.h>
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#define MSR_IA32_PERF_STATUS 0x00000198
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#define MSR_IA32_PERF_CTL 0x00000199
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#define MSR_IA32_MISC_ENABLE 0x000001a0
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static int c7a_speed_translation[] = {
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// LFM HFM
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0x0409, 0x0f13, // 400MHz, 844mV --> 1500MHz, 1.004V C7-M
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0x0409, 0x1018, // 400MHz, 844mV --> 1600MHz, 1.084V
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0x0409, 0x0c18, // 533MHz, 844mV --> 1600MHz, 1.084V
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0x0409, 0x121c, // 400MHz, 844mV --> 1800MHz, 1.148V
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0x0409, 0x0e1c, // 533MHz, 844mV --> 1860MHz, 1.148V
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0x0409, 0x141f, // 400MHz, 844mV --> 2000MHz, 1.196V
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0x0409, 0x0f1f, // 533MHz, 844mV --> 2000MHz, 1.196V
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0x0406, 0x0a06, // 400MHz, 796mV --> 1000MHz, 796mV C7-M ULV
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0x0406, 0x0a09, // 400MHz, 796mV --> 1000MHz, 844mV
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0x0406, 0x0c09, // 400MHz, 796mV --> 1200MHz, 844mV
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0x0406, 0x0f10, // 400MHz, 796mV --> 1500MHz, 956mV
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};
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static int c7d_speed_translation[] = {
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// LFM HFM
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0x0409, 0x1018, // 400MHz, 844mV --> 1600MHz, 1.084V C7-M
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0x0409, 0x121f, // 400MHz, 844mV --> 1800MHz, 1.196V
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0x0809, 0x121f, // 800MHz, 844mV --> 1800MHz, 1.196V
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0x0409, 0x141f, // 400MHz, 844mV --> 2000MHz, 1.196V
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0x0809, 0x141f, // 800MHz, 844mV --> 2000MHz, 1.196V
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0x0406, 0x0806, // 400MHz, 796mV --> 800MHz, 796mV C7-M ULV
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0x0406, 0x0a06, // 400MHz, 796mV --> 1000MHz, 796mV
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0x0406, 0x0c09, // 400MHz, 796mV --> 1200MHz, 844mV
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0x0806, 0x0c09, // 800MHz, 796mV --> 1200MHz, 844mV
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0x0406, 0x0f10, // 400MHz, 796mV --> 1500MHz, 956mV
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0x0806, 0x1010, // 800MHz, 796mV --> 1600MHz, 956mV
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};
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static void set_c7_speed(int model) {
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int cnt, current, new, i;
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msr_t msr;
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printk(BIOS_DEBUG, "Enabling improved C7 clock and voltage.\n");
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// Enable Speedstep
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msr = rdmsr(MSR_IA32_MISC_ENABLE);
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msr.lo |= (1 << 16);
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wrmsr(MSR_IA32_MISC_ENABLE, msr);
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msr = rdmsr(MSR_IA32_PERF_STATUS);
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printk(BIOS_INFO, "Voltage: %dmV (min %dmV; max %dmV)\n",
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((int)(msr.lo & 0xff) * 16 + 700),
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((int)((msr.hi >> 16) & 0xff) * 16 + 700),
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((int)(msr.hi & 0xff) * 16 + 700));
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printk(BIOS_INFO, "CPU multiplier: %dx (min %dx; max %dx)\n",
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(int)((msr.lo >> 8) & 0xff),
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(int)((msr.hi >> 24) & 0xff), (int)((msr.hi >> 8) & 0xff));
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printk(BIOS_DEBUG, " msr.lo = %x\n", msr.lo);
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/* Wait while CPU is busy */
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cnt = 0;
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while (msr.lo & ((1 << 16) | (1 << 17))) {
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udelay(16);
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msr = rdmsr(MSR_IA32_PERF_STATUS);
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cnt++;
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if (cnt > 128) {
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printk(BIOS_WARNING, "Could not update multiplier and voltage.\n");
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return;
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}
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}
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current = msr.lo & 0xffff;
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// Start out with no change.
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new = current;
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switch (model) {
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case 10: // model A
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for (i = 0; i < ARRAY_SIZE(c7a_speed_translation); i += 2) {
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if ((c7a_speed_translation[i] == current) &&
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((c7a_speed_translation[i + 1] & 0xff00) ==
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(msr.hi & 0xff00))) {
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new = c7a_speed_translation[i + 1];
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}
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}
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break;
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case 13: // model D
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for (i = 0; i < ARRAY_SIZE(c7d_speed_translation); i += 2) {
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if ((c7d_speed_translation[i] == current) &&
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((c7d_speed_translation[i + 1] & 0xff00) ==
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(msr.hi & 0xff00))) {
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new = c7d_speed_translation[i + 1];
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}
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}
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break;
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default:
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printk(BIOS_INFO, "CPU type not known, multiplier unchanged.\n");
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}
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msr.lo = new;
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msr.hi = 0;
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printk(BIOS_DEBUG, " new msr.lo = %x\n", msr.lo);
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wrmsr(MSR_IA32_PERF_CTL, msr);
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/* Wait until the power transition ends */
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cnt = 0;
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do {
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udelay(16);
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msr = rdmsr(MSR_IA32_PERF_STATUS);
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cnt++;
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if (cnt > 128) {
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printk(BIOS_WARNING, "Error while updating multiplier and voltage\n");
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break;
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}
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} while (msr.lo & ((1 << 16) | (1 << 17)));
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printk(BIOS_INFO, "Current voltage: %dmV\n", ((int)(msr.lo & 0xff) * 16 + 700));
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printk(BIOS_INFO, "Current CPU multiplier: %dx\n", (int)((msr.lo >> 8) & 0xff));
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}
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static void c7_init(struct device *dev)
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{
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u8 brand;
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struct cpuinfo_x86 c;
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msr_t msr;
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get_fms(&c, dev->device);
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printk(BIOS_INFO, "Detected VIA ");
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switch (c.x86_model) {
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case 10:
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msr = rdmsr(0x1153);
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brand = (((msr.lo >> 2) ^ msr.lo) >> 18) & 3;
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printk(BIOS_INFO, "Model A ");
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break;
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case 13:
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msr = rdmsr(0x1154);
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brand = (((msr.lo >> 4) ^ (msr.lo >> 2))) & 0x000000ff;
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printk(BIOS_INFO, "Model D ");
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break;
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default:
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printk(BIOS_INFO, "Model Unknown ");
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brand = 0xff;
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}
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switch (brand) {
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case 0:
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printk(BIOS_INFO, "C7-M\n");
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break;
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case 1:
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printk(BIOS_INFO, "C7\n");
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break;
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case 2:
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printk(BIOS_INFO, "Eden\n");
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break;
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case 3:
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printk(BIOS_INFO, "C7-D\n");
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break;
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default:
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printk(BIOS_INFO, "%02x (please report)\n", brand);
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}
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/* Gear up */
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set_c7_speed(c.x86_model);
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/* Enable APIC */
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msr = rdmsr(0x1107);
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msr.lo |= 1 << 24;
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wrmsr(0x1107, msr);
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/* Turn on cache */
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x86_enable_cache();
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/* Set up Memory Type Range Registers */
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x86_setup_mtrrs();
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x86_mtrr_check();
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/* Enable the local CPU APICs */
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setup_lapic();
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};
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static struct device_operations cpu_dev_ops = {
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.init = c7_init,
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};
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/* Look in arch/x86/lib/cpu.c:cpu_initialize. If there is no CPU with an exact
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* ID, the CPU mask (stepping) is masked out and the check is repeated. This
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* allows us to keep the table significantly smaller.
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*/
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static const struct cpu_device_id cpu_table[] = {
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{X86_VENDOR_CENTAUR, 0x06A0}, // VIA C7 Esther
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{X86_VENDOR_CENTAUR, 0x06A9}, // VIA C7 Esther
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{X86_VENDOR_CENTAUR, 0x06D0}, // VIA C7-M
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{0, 0},
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};
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static const struct cpu_driver driver __cpu_driver = {
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.ops = &cpu_dev_ops,
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.id_table = cpu_table,
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};
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