arch/mips: simplify cache operations
Cache operations are simplified by removing assembly
implementation and replacing it with simpler C code.
BUG=chrome-os-partner:31438
TEST=tested on Pistachio bring up board; caches are properly
invalidated;
BRANCH=none
Change-Id: I0f092660549c368e98c208ae0c991fe6f5a428d7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bf99849e75813cba865b15af9e110687816e61e4
Original-Change-Id: I965e7929718424f92f3556369d36a18ef67aa0d0
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/250792
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9820
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Ionela Voinescu
Patrick Georgi
parent
8cc3a2a467
commit
ef4e87b45b
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@ -18,46 +18,9 @@
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*/
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#include <arch/cache.h>
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#include <symbols.h>
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#include <arch/cpu.h>
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#include <console/console.h>
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/* Cache operations */
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/*
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* __get_line_size:
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* Read config register
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* Isolate instruction cache line size
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* Interpret value as per MIPS manual: 2 << value
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* Return cache line size
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*/
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#define __get_line_size(cfg_no, cfg_sel, lshift, nobits) \
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({ int __res; \
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__asm__ __volatile__( \
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".set push\n\t" \
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".set noreorder\n\t" \
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".set mips32\n\t" \
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"mfc0 $t5, "#cfg_no"," #cfg_sel"\n\t" \
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".set mips0\n\t" \
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"ext $t6, $t5," #lshift"," #nobits"\n\t" \
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"li $t7, 2\n\t" \
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"sllv %0, $t7, $t6\n\t" \
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".set pop\n\t" \
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: "=r" (__res)); \
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__res; \
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})
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/* clear_L2tag: clear L23Tag register */
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#define clear_L2tag() \
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({ \
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__asm__ __volatile__( \
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".set push\n\t" \
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".set noreorder\n\t" \
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".set mips32\n\t" \
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"mtc0 $zero, $28, 4\n\t" \
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".set mips0\n\t" \
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".set pop\n\t" \
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); \
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})
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#include <symbols.h>
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/* cache_op: issues cache operation for specified address */
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#define cache_op(op, addr) \
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@ -73,12 +36,32 @@
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: "i" (op), "R" (*(unsigned char *)(addr))); \
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})
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static int get_cache_line(uint8_t type)
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#define MIPS_CONFIG1_DL_SHIFT 10
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#define MIPS_CONFIG1_DL_MASK (0x00000007)
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#define MIPS_CONFIG1_IL_SHIFT 19
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#define MIPS_CONFIG1_IL_MASK (0x00000007)
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#define MIPS_CONFIG2_SL_SHIFT 4
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#define MIPS_CONFIG2_SL_MASK (0x0000000F)
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/*
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* get_cache_line_size:
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* Read config register
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* Isolate instruction cache line size
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* Interpret value as per MIPS manual: 2 << value
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* Return cache line size
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*/
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static int get_cache_line_size(uint8_t type)
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{
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switch (type) {
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case ICACHE: return get_icache_line();
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case DCACHE: return get_dcache_line();
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case L2CACHE: return get_L2cache_line();
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case ICACHE:
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return 2 << ((read_c0_config1() >> MIPS_CONFIG1_IL_SHIFT) &
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MIPS_CONFIG1_IL_MASK);
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case DCACHE:
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return 2 << ((read_c0_config1() >> MIPS_CONFIG1_DL_SHIFT) &
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MIPS_CONFIG1_DL_MASK);
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case L2CACHE:
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return 2 << ((read_c0_config2() >> MIPS_CONFIG2_SL_SHIFT) &
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MIPS_CONFIG2_SL_MASK);
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default:
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printk(BIOS_ERR, "%s: Error: unsupported cache type.\n",
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__func__);
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@ -92,7 +75,7 @@ void perform_cache_operation(uintptr_t start, size_t size, uint8_t operation)
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u32 line_size, line_mask;
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uintptr_t end;
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line_size = get_cache_line((operation >> CACHE_TYPE_SHIFT) &
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line_size = get_cache_line_size((operation >> CACHE_TYPE_SHIFT) &
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CACHE_TYPE_MASK);
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if (!line_size)
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return;
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@ -100,7 +83,7 @@ void perform_cache_operation(uintptr_t start, size_t size, uint8_t operation)
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end = (start + (line_size - 1) + size) & line_mask;
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start &= line_mask;
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if ((operation & L2CACHE) == L2CACHE)
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clear_L2tag();
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write_c0_l23taglo(0);
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while (start < end) {
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switch (operation) {
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case CACHE_CODE(ICACHE, WB_INVD):
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@ -23,10 +23,6 @@
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#include <stddef.h>
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#include <stdint.h>
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#define get_icache_line() __get_line_size($16, 1, 19, 3)
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#define get_dcache_line() __get_line_size($16, 1, 10, 3)
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#define get_L2cache_line() __get_line_size($16, 2, 4, 4)
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#define CACHE_TYPE_SHIFT (0)
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#define CACHE_OP_SHIFT (2)
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#define CACHE_TYPE_MASK (0x3)
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@ -106,6 +106,13 @@ do { \
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#define read_c0_config1() __read_32bit_c0_register($16, 1)
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#define write_c0_config1(val) __write_32bit_c0_register($16, 1, (val))
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#define read_c0_config2() __read_32bit_c0_register($16, 2)
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#define write_c0_config2(val) __write_32bit_c0_register($16, 2, (val))
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#define read_c0_l23taglo() __read_32bit_c0_register($28, 4)
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#define write_c0_l23taglo(val) __write_32bit_c0_register($28, 4, (val))
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#define C0_ENTRYLO_PFN_SHIFT 6
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#define C0_ENTRYLO_WB (0x3 << 3) /* Cacheable, write-back, non-coherent */
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#define C0_ENTRYLO_D (0x1 << 2) /* Writeable */
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