mb/google/asurada: Improve boot time by raising little CPU frequency
Raise little CPU to 2GHz at romstage to improve boot time. BUG=b:177389446 TEST=observe boot time by `cbmem` Before: 1,062,359 us After: 907,458 us Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: I723a916d7f708627525ef11e3c5ea0b381f269aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/49935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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@ -2,11 +2,14 @@
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#include <arch/stages.h>
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#include <console/console.h>
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#include <delay.h>
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#include <fmap.h>
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#include <soc/dramc_param.h>
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#include <soc/emi.h>
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#include <soc/mmu_operations.h>
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#include <soc/mt6315.h>
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#include <soc/mt6359p.h>
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#include <soc/pll_common.h>
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/* This must be defined in chromeos.fmd in same name and size. */
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#define CALIBRATION_REGION "RW_DDR_TRAINING"
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@ -42,9 +45,20 @@ static struct dramc_param_ops dparam_ops = {
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.write_to_flash = &write_calibration_data_to_flash,
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};
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static void raise_little_cpu_freq(void)
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{
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mt6359p_buck_set_voltage(MT6359P_SRAM_PROC2, 1000 * 1000);
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mt6315_buck_set_voltage(MT6315_CPU, MT6315_BUCK_3, 925 * 1000);
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udelay(200);
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mt_pll_raise_little_cpu_freq(2000 * MHz);
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mt_pll_raise_cci_freq(1400 * MHz);
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}
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void platform_romstage_main(void)
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{
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mt6359p_romstage_init();
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mt6315_romstage_init();
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raise_little_cpu_freq();
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mt_mem_init(&dparam_ops);
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mtk_mmu_after_dram();
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}
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@ -36,10 +36,12 @@ romstage-y += ../common/gpio.c gpio.c
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romstage-y += ../common/i2c.c i2c.c
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romstage-y += ../common/mmu_operations.c mmu_operations.c
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romstage-y += memory.c dramc_param.c ../common/memory_test.c
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romstage-y += ../common/pll.c pll.c
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romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
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romstage-y += ../common/timer.c
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romstage-y += ../common/uart.c
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romstage-y += pmif.c pmif_clk.c pmif_spi.c pmif_spmi.c
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romstage-y += mt6315.c
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romstage-y += mt6359p.c
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ramstage-y += ../common/auxadc.c
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