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mb/intel/adlrvp_m: Enable HECI1 communication 

The patch enables HECI1 interface to allow OS applications to communicate
with CSE.

TEST=Verify PCI device 0:16.0 exposed in the lspci output

Signed-off-by: zhixingma <zhixing.ma@intel.com>
Change-Id: Ifd338345caa183f03097f1003080992da70296ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
This commit is contained in:
zhixingma 2021-09-21 10:39:52 -07:00 committed by Felix Held
parent 7011fa1135
commit ef8654554f
1 changed files with 3 additions and 0 deletions
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3
src/mainboard/intel/adlrvp/devicetree_m.cb
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@ -27,6 +27,9 @@ chip soc/intel/alderlake
register "pmc_gpe0_dw1" = "GPP_D" register "pmc_gpe0_dw1" = "GPP_D"
register "pmc_gpe0_dw2" = "GPP_E" register "pmc_gpe0_dw2" = "GPP_E"
# Enable HECI1 communication
register "HeciEnabled" = "1"
# FSP configuration # FSP configuration
register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-C port 0 register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-C port 0
register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-C port 1 register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-C port 1