nb/intel/sandybridge: Unify the code paths
The code for Sandy Bridge is a subset of the code for Ivy Bridge. Adapt the Ivy Bridge code so that it also supports Sandy Bridge, and use it. Tested on Asus P8Z77-V LX2, still boots with i7-2600 and i5-3330. Change-Id: I7b78ec605aff976b9a5cdbb364a69df4b4947c6e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39737 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -214,14 +214,6 @@ static void save_timings(ramctr_timing *ctrl)
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mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, ctrl, sizeof(*ctrl));
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mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, ctrl, sizeof(*ctrl));
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}
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}
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static int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_uma_size)
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{
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if (IS_SANDY_CPU(ctrl->cpu))
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return try_init_dram_ddr3_snb(ctrl, fast_boot, s3resume, me_uma_size);
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else
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return try_init_dram_ddr3_ivb(ctrl, fast_boot, s3resume, me_uma_size);
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}
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static void init_dram_ddr3(int min_tck, int s3resume, const u32 cpuid)
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static void init_dram_ddr3(int min_tck, int s3resume, const u32 cpuid)
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{
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{
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int me_uma_size, cbmem_was_inited, fast_boot, err;
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int me_uma_size, cbmem_was_inited, fast_boot, err;
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@ -179,8 +179,8 @@ void set_read_write_timings(ramctr_timing *ctrl);
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void set_normal_operation(ramctr_timing *ctrl);
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void set_normal_operation(ramctr_timing *ctrl);
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void final_registers(ramctr_timing *ctrl);
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void final_registers(ramctr_timing *ctrl);
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void restore_timings(ramctr_timing *ctrl);
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void restore_timings(ramctr_timing *ctrl);
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int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_uma_size);
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int try_init_dram_ddr3_snb(ramctr_timing *ctrl, int fast_boot, int s3_resume, int me_uma_size);
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int try_init_dram_ddr3_snb(ramctr_timing *ctrl, int fast_boot, int s3_resume, int me_uma_size);
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int try_init_dram_ddr3_ivb(ramctr_timing *ctrl, int fast_boot, int s3_resume, int me_uma_size);
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#endif
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#endif
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@ -10,6 +10,8 @@
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#include "raminit_common.h"
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#include "raminit_common.h"
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#include "raminit_tables.h"
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#include "raminit_tables.h"
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#define SNB_MIN_DCLK_133_MULT 3
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#define SNB_MAX_DCLK_133_MULT 8
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#define IVB_MIN_DCLK_133_MULT 3
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#define IVB_MIN_DCLK_133_MULT 3
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#define IVB_MAX_DCLK_133_MULT 10
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#define IVB_MAX_DCLK_133_MULT 10
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#define IVB_MIN_DCLK_100_MULT 7
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#define IVB_MIN_DCLK_100_MULT 7
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@ -26,6 +28,10 @@ static u32 get_FRQ(const ramctr_timing *ctrl)
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if (ctrl->base_freq == 133)
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if (ctrl->base_freq == 133)
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return clamp_u32(IVB_MIN_DCLK_133_MULT, FRQ, IVB_MAX_DCLK_133_MULT);
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return clamp_u32(IVB_MIN_DCLK_133_MULT, FRQ, IVB_MAX_DCLK_133_MULT);
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} else if (IS_SANDY_CPU(ctrl->cpu)) {
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if (ctrl->base_freq == 133)
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return clamp_u32(SNB_MIN_DCLK_133_MULT, FRQ, SNB_MAX_DCLK_133_MULT);
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}
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}
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die("Unsupported CPU or base frequency.");
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die("Unsupported CPU or base frequency.");
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@ -121,7 +127,7 @@ static u32 get_COMP2(u32 FRQ, u8 base_freq)
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return frq_comp2_map[0][FRQ - 3];
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return frq_comp2_map[0][FRQ - 3];
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}
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}
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static void ivb_normalize_tclk(ramctr_timing *ctrl, bool ref_100mhz_support)
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static void normalize_tclk(ramctr_timing *ctrl, bool ref_100mhz_support)
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{
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{
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if (ctrl->tCK <= TCK_1200MHZ) {
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if (ctrl->tCK <= TCK_1200MHZ) {
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ctrl->tCK = TCK_1200MHZ;
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ctrl->tCK = TCK_1200MHZ;
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@ -164,7 +170,7 @@ static void ivb_normalize_tclk(ramctr_timing *ctrl, bool ref_100mhz_support)
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if (!ref_100mhz_support && ctrl->base_freq == 100) {
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if (!ref_100mhz_support && ctrl->base_freq == 100) {
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/* Skip unsupported frequency */
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/* Skip unsupported frequency */
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ctrl->tCK++;
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ctrl->tCK++;
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ivb_normalize_tclk(ctrl, ref_100mhz_support);
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normalize_tclk(ctrl, ref_100mhz_support);
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}
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}
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}
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}
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@ -188,7 +194,7 @@ static void find_cas_tck(ramctr_timing *ctrl)
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* Normalising tCK before computing clock could potentially
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* Normalising tCK before computing clock could potentially
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* result in a lower selected CAS, which is desired.
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* result in a lower selected CAS, which is desired.
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*/
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*/
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ivb_normalize_tclk(ctrl, ref_100mhz_support);
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normalize_tclk(ctrl, ref_100mhz_support);
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if (!(ctrl->tCK))
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if (!(ctrl->tCK))
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die("Couldn't find compatible clock / CAS settings\n");
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die("Couldn't find compatible clock / CAS settings\n");
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@ -218,6 +224,10 @@ static void find_cas_tck(ramctr_timing *ctrl)
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static void dram_timing(ramctr_timing *ctrl)
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static void dram_timing(ramctr_timing *ctrl)
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{
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{
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/*
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* On Sandy Bridge, the maximum supported DDR3 frequency is 1066MHz (DDR3 2133).
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* Cap it for faster DIMMs, and align it to the closest JEDEC standard frequency.
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*/
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/*
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/*
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* On Ivy Bridge, the maximum supported DDR3 frequency is 1400MHz (DDR3 2800).
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* On Ivy Bridge, the maximum supported DDR3 frequency is 1400MHz (DDR3 2800).
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* Cap it at 1200MHz (DDR3 2400), and align it to the closest JEDEC standard frequency.
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* Cap it at 1200MHz (DDR3 2400), and align it to the closest JEDEC standard frequency.
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@ -482,11 +492,13 @@ static void dram_ioregs(ramctr_timing *ctrl)
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printram("done\n");
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printram("done\n");
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}
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}
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int try_init_dram_ddr3_ivb(ramctr_timing *ctrl, int fast_boot, int s3_resume, int me_uma_size)
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int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_uma_size)
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{
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{
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int err;
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int err;
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printk(BIOS_DEBUG, "Starting Ivybridge RAM training (%d).\n", fast_boot);
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printk(BIOS_DEBUG, "Starting %s Bridge RAM training (%s).\n",
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IS_SANDY_CPU(ctrl->cpu) ? "Sandy" : "Ivy",
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fast_boot ? "fast boot" : "full initialization");
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if (!fast_boot) {
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if (!fast_boot) {
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/* Find fastest common supported parameters */
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/* Find fastest common supported parameters */
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@ -592,7 +604,7 @@ int try_init_dram_ddr3_ivb(ramctr_timing *ctrl, int fast_boot, int s3_resume, in
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write_controller_mr(ctrl);
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write_controller_mr(ctrl);
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if (!s3_resume) {
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if (!s3resume) {
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err = channel_test(ctrl);
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err = channel_test(ctrl);
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if (err)
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if (err)
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return err;
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return err;
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