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mb/intel/tglrvp: Update TCSS D3Hot and D3Cold configuration 

It is expected both of TCSS D3Hot and D3Cold are enabled by default.

BUG=None
TEST=Verified both of TCSS D3Hot and D3Cold configuration on TGLRVP.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Id569d8191f82f12379b57a9c50aec31776220bb5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
This commit is contained in:
John Zhao 2020-07-28 11:36:07 -07:00 committed by Nick Vaccaro
parent 5fdf2760a5
commit efcfaa8b6c
2 changed files with 0 additions and 8 deletions
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4
src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
View File

@ -117,10 +117,6 @@ chip soc/intel/tigerlake
# Enable S0ix
register "s0ix_enable" = "1"
# D3Hot and D3Cold for TCSS
register "TcssD3HotEnable" = "1"
register "TcssD3ColdEnable" = "1"
#HD Audio
register "PchHdaDspEnable" = "1"
register "PchHdaAudioLinkHdaEnable" = "0"

4
src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
View File

@ -113,10 +113,6 @@ chip soc/intel/tigerlake
# Enable S0ix
register "s0ix_enable" = "1"
# D3Hot and D3Cold for TCSS
register "TcssD3HotEnable" = "1"
register "TcssD3ColdEnable" = "1"
#HD Audio
register "PchHdaDspEnable" = "1"
register "PchHdaAudioLinkHdaEnable" = "0"