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stout: Support native raminit 

Change-Id: If64607d40a64ada8cfe4c3ad054be9d6571fc221
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13660
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Vladimir Serbinenko 2016-02-10 02:42:16 +01:00 committed by Martin Roth
parent 144eea0697
commit f004b6b927
3 changed files with 27 additions and 4 deletions
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4
src/mainboard/google/stout/Kconfig
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@ -17,10 +17,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select INTEL_INT15 select INTEL_INT15
select IVYBRIDGE_LVDS select IVYBRIDGE_LVDS
config USE_NATIVE_RAMINIT
bool
default n
config CHROMEOS config CHROMEOS
select CHROMEOS_VBNV_CMOS select CHROMEOS_VBNV_CMOS

2
src/mainboard/google/stout/devicetree.cb
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@ -20,6 +20,8 @@ chip northbridge/intel/sandybridge
register "gpu_cpu_backlight" = "0x1155" register "gpu_cpu_backlight" = "0x1155"
register "gpu_pch_backlight" = "0x06100610" register "gpu_pch_backlight" = "0x06100610"
register "max_mem_clock_mhz" = "666"
device cpu_cluster 0 on device cpu_cluster 0 on
chip cpu/intel/socket_rPGA989 chip cpu/intel/socket_rPGA989
device lapic 0 on end device lapic 0 on end

25
src/mainboard/google/stout/romstage.c
View File

@ -28,6 +28,7 @@
#include <console/console.h> #include <console/console.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>
#include <arch/cpu.h> #include <arch/cpu.h>
#include <cpu/x86/msr.h> #include <cpu/x86/msr.h>
@ -138,6 +139,12 @@ static void early_ec_init(void)
} }
} }
void mainboard_get_spd(spd_raw_data *spd)
{
read_spd(&spd[0], 0x50);
read_spd(&spd[2], 0x52);
}
void mainboard_fill_pei_data(struct pei_data *pei_data) void mainboard_fill_pei_data(struct pei_data *pei_data)
{ {
struct pei_data pei_data_template = { struct pei_data pei_data_template = {
@ -209,3 +216,21 @@ int mainboard_should_reset_usb(int s3resume)
void mainboard_config_superio(void) void mainboard_config_superio(void)
{ {
} }
const struct southbridge_usb_port mainboard_usb_ports[] = {
/* enabled usb oc pin length */
{1, 0, 0}, /* P0: USB 3.0 1 (OC0) */
{1, 0, 0}, /* P1: USB 3.0 2 (OC0) */
{0, 0, 0}, /* P2: Empty */
{1, 0, -1}, /* P3: Camera (no OC) */
{1, 0, -1}, /* P4: WLAN (no OC) */
{1, 0, -1}, /* P5: WWAN (no OC) */
{0, 0, 0}, /* P6: Empty */
{0, 0, 0}, /* P7: Empty */
{0, 0, 0}, /* P8: Empty */
{1, 0, 4}, /* P9: USB 2.0 (AUO4) (OC4) */
{0, 0, 0}, /* P10: Empty */
{0, 0, 0}, /* P11: Empty */
{0, 0, 0}, /* P12: Empty */
{1, 0, -1}, /* P13: Bluetooth (no OC) */
};