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Inagua: Indent and wihtespace cleanup 

Change-Id: Ie574e08f138c88084c8ce06d0d0acc489013e3d7
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Reviewed-on: http://review.coreboot.org/547
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
This commit is contained in:
Kerry Sheh 2012-01-19 13:25:55 +08:00 committed by Marc Jones
parent 19329c90d3
commit f03360f3f8
16 changed files with 1076 additions and 1080 deletions
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1
src/mainboard/amd/inagua/Kconfig
View File

@ -137,6 +137,5 @@ config SB800_AHCI_ROM
bool
default n
endif # BOARD_AMD_INAGUA

12
src/mainboard/amd/inagua/PlatformGnbPcie.c
View File

@ -54,7 +54,7 @@ OemCustomizeInitEarly (
ALLOCATE_HEAP_PARAMS AllocHeapParams;
PCIe_PORT_DESCRIPTOR PortList [] = {
PCIe_PORT_DESCRIPTOR PortList [] = {
// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) MXM
{
0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
@ -79,9 +79,9 @@ PCIe_PORT_DESCRIPTOR PortList [] = {
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
}
};
};
PCIe_DDI_DESCRIPTOR DdiList [] = {
PCIe_DDI_DESCRIPTOR DdiList [] = {
// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) DP0 to LVDS
{
0, //Descriptor flags
@ -94,14 +94,14 @@ PCIe_DDI_DESCRIPTOR DdiList [] = {
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeAutoDetect, Aux2, Hdp2)
}
};
};
PCIe_COMPLEX_DESCRIPTOR Brazos = {
PCIe_COMPLEX_DESCRIPTOR Brazos = {
DESCRIPTOR_TERMINATE_LIST,
0,
&PortList[0],
&DdiList[0]
};
};
// GNB PCIe topology Porting

15
src/mainboard/amd/inagua/PlatformGnbPcieComplex.h
View File

@ -29,7 +29,7 @@
#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port5
@ -37,7 +37,7 @@
#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port6
@ -45,7 +45,7 @@
#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port7
@ -53,7 +53,7 @@
#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port8
@ -61,12 +61,9 @@
#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
VOID
OemCustomizeInitEarly (
IN OUT AMD_EARLY_PARAMS *InitEarly
);
VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly);
#endif //_PLATFORM_GNB_PCIE_COMPLEX_H

2
src/mainboard/amd/inagua/agesawrapper.c
View File

@ -209,7 +209,7 @@ agesawrapper_amdinitreset (
if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
AmdReleaseStruct (&AmdParamStruct);
return (UINT32)status;
}
}
UINT32
agesawrapper_amdinitearly (

12
src/mainboard/amd/inagua/buildOpts.c
View File

@ -89,12 +89,12 @@
#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
#define BLDOPT_REMOVE_ACPI_PSTATES FALSE
#define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE
#define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE
#define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE
#define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE
#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE
#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE
#define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE
#define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE
#define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE
#define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE
#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE
#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE
#define BLDOPT_REMOVE_SRAT FALSE
#define BLDOPT_REMOVE_SLIT FALSE
#define BLDOPT_REMOVE_WHEA FALSE

16
src/mainboard/amd/inagua/dimmSpd.c
View File

@ -26,19 +26,19 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA
#define DIMENSION(array)(sizeof (array)/ sizeof (array [0]))
/*#pragma optimize ("", off) // for source level debug
*---------------------------------------------------------------------------
*
* SPD address table - porting required
*/
*---------------------------------------------------------------------------
*
* SPD address table - porting required
*/
static const UINT8 spdAddressLookup [1] [2] [2] = // socket, channel, dimm
{
{
// socket 0
{
{0xA0, 0xA2}, // channel 0 dimms
{0x00, 0x00}, // channel 1 dimms
},
};
};
/*-----------------------------------------------------------------------------
*
@ -129,10 +129,10 @@ static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count)
}
static void writePmReg (int reg, int data)
{
{
__outbyte (0xCD6, reg);
__outbyte (0xCD7, data);
}
}
static void setupFch (int ioBase)
{

16
src/mainboard/amd/inagua/get_bus_conf.c
View File

@ -31,17 +31,17 @@
/* Global variables for MB layouts and these will be shared by irqtable mptable
* and acpi_tables busnum is default.
*/
* and acpi_tables busnum is default.
*/
u8 bus_isa;
u8 bus_sb800[3];
u32 apicid_sb800;
/*
* Here you only need to set value in pci1234 for HT-IO that could be installed or not
* You may need to preset pci1234 for HTIO board,
* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
*/
* Here you only need to set value in pci1234 for HT-IO that could be installed or not
* You may need to preset pci1234 for HTIO board,
* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
*/
u32 pci1234x[] = {
0x0000ff0,
};
@ -65,7 +65,7 @@ void get_bus_conf(void)
get_bus_conf_done = 1;
/*
/*
* This is the call to AmdInitLate. It is really in the wrong place, conceptually,
* but functionally within the coreboot model, this is the best place to make the
* call. The logically correct place to call AmdInitLate is after PCI scan is done,
@ -97,7 +97,7 @@ void get_bus_conf(void)
bus_type[0] = 1; /* pci */
// bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff;
// bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff;
bus_sb800[0] = (pci1234x[0] >> 16) & 0xff;
/* sb800 */

4
src/mainboard/amd/inagua/mainboard.c
View File

@ -74,8 +74,8 @@ void set_pcie_dereset(void)
uint64_t uma_memory_base, uma_memory_size;
/*************************************************
* enable the dedicated function in INAGUA board.
*************************************************/
* enable the dedicated function in INAGUA board.
*************************************************/
static void inagua_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");

8
src/mainboard/amd/inagua/platform_cfg.h
View File

@ -38,13 +38,13 @@
*/
#ifndef BIOS_SIZE
#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
#define BIOS_SIZE BIOS_SIZE_1M
#define BIOS_SIZE BIOS_SIZE_1M
#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
#define BIOS_SIZE BIOS_SIZE_2M
#define BIOS_SIZE BIOS_SIZE_2M
#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1
#define BIOS_SIZE BIOS_SIZE_4M
#define BIOS_SIZE BIOS_SIZE_4M
#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1
#define BIOS_SIZE BIOS_SIZE_8M
#define BIOS_SIZE BIOS_SIZE_8M
#endif
#endif