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Inagua: Indent and wihtespace cleanup 

Change-Id: Ie574e08f138c88084c8ce06d0d0acc489013e3d7
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Reviewed-on: http://review.coreboot.org/547
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
This commit is contained in:
Kerry Sheh 2012-01-19 13:25:55 +08:00 committed by Marc Jones
parent 19329c90d3
commit f03360f3f8
16 changed files with 1076 additions and 1080 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

890
src/mainboard/amd/inagua/BiosCallOuts.c
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File diff suppressed because it is too large Load Diff

12
src/mainboard/amd/inagua/BiosCallOuts.h
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@ -28,15 +28,15 @@
#define BIOS_HEAP_SIZE 0x20000 /* 64MB */ #define BIOS_HEAP_SIZE 0x20000 /* 64MB */
typedef struct _BIOS_HEAP_MANAGER { typedef struct _BIOS_HEAP_MANAGER {
//UINT32 AvailableSize; //UINT32 AvailableSize;
UINT32 StartOfAllocatedNodes; UINT32 StartOfAllocatedNodes;
UINT32 StartOfFreedNodes; UINT32 StartOfFreedNodes;
} BIOS_HEAP_MANAGER; } BIOS_HEAP_MANAGER;
typedef struct _BIOS_BUFFER_NODE { typedef struct _BIOS_BUFFER_NODE {
UINT32 BufferHandle; UINT32 BufferHandle;
UINT32 BufferSize; UINT32 BufferSize;
UINT32 NextNodeOffset; UINT32 NextNodeOffset;
} BIOS_BUFFER_NODE; } BIOS_BUFFER_NODE;
/* /*
* CALLOUTS * CALLOUTS

135
src/mainboard/amd/inagua/Kconfig
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@ -20,108 +20,108 @@
if BOARD_AMD_INAGUA if BOARD_AMD_INAGUA
config BOARD_SPECIFIC_OPTIONS # dummy config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y def_bool y
select ARCH_X86 select ARCH_X86
select CPU_AMD_AGESA_FAMILY14 select CPU_AMD_AGESA_FAMILY14
select NORTHBRIDGE_AMD_AGESA_FAMILY14_ROOT_COMPLEX select NORTHBRIDGE_AMD_AGESA_FAMILY14_ROOT_COMPLEX
select NORTHBRIDGE_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14
select SOUTHBRIDGE_AMD_CIMX_SB800 select SOUTHBRIDGE_AMD_CIMX_SB800
select SUPERIO_SMSC_KBC1100 select SUPERIO_SMSC_KBC1100
select BOARD_HAS_FADT select BOARD_HAS_FADT
select HAVE_BUS_CONFIG select HAVE_BUS_CONFIG
select HAVE_OPTION_TABLE select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE select HAVE_MP_TABLE
select HAVE_MAINBOARD_RESOURCES select HAVE_MAINBOARD_RESOURCES
select HAVE_HARD_RESET select HAVE_HARD_RESET
select SB_HT_CHAIN_UNITID_OFFSET_ONLY select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select LIFT_BSP_APIC_ID select LIFT_BSP_APIC_ID
select SERIAL_CPU_INIT select SERIAL_CPU_INIT
select AMDMCT select AMDMCT
select HAVE_ACPI_TABLES select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_2048 select BOARD_ROMSIZE_KB_2048
select ENABLE_APIC_EXT_ID select ENABLE_APIC_EXT_ID
select GFXUMA select GFXUMA
config AMD_AGESA config AMD_AGESA
bool bool
default y default y
config MAINBOARD_DIR config MAINBOARD_DIR
string string
default amd/inagua default amd/inagua
config APIC_ID_OFFSET config APIC_ID_OFFSET
hex hex
default 0x0 default 0x0
config MAINBOARD_PART_NUMBER config MAINBOARD_PART_NUMBER
string string
default "Inagua" default "Inagua"
config HW_MEM_HOLE_SIZEK config HW_MEM_HOLE_SIZEK
hex hex
default 0x200000 default 0x200000
config MAX_CPUS config MAX_CPUS
int int
default 2 default 2
config MAX_PHYSICAL_CPUS config MAX_PHYSICAL_CPUS
int int
default 1 default 1
config HW_MEM_HOLE_SIZE_AUTO_INC config HW_MEM_HOLE_SIZE_AUTO_INC
bool bool
default n default n
config MEM_TRAIN_SEQ config MEM_TRAIN_SEQ
int int
default 2 default 2
config IRQ_SLOT_COUNT config IRQ_SLOT_COUNT
int int
default 11 default 11
config RAMTOP config RAMTOP
hex hex
default 0x1000000 default 0x1000000
config HEAP_SIZE config HEAP_SIZE
hex hex
default 0xc0000 default 0xc0000
config STACK_SIZE config STACK_SIZE
hex hex
default 0x10000 default 0x10000
config ACPI_SSDTX_NUM config ACPI_SSDTX_NUM
int int
default 0 default 0
config RAMBASE config RAMBASE
hex hex
default 0x200000 default 0x200000
config SIO_PORT config SIO_PORT
hex hex
default 0x2e default 0x2e
config DRIVERS_PS2_KEYBOARD config DRIVERS_PS2_KEYBOARD
bool bool
default y default y
config WARNINGS_ARE_ERRORS config WARNINGS_ARE_ERRORS
bool bool
default n default n
config ONBOARD_VGA_IS_PRIMARY config ONBOARD_VGA_IS_PRIMARY
bool bool
default y default y
config VGA_BIOS config VGA_BIOS
bool bool
default n default n
#config VGA_BIOS_FILE #config VGA_BIOS_FILE
# string "VGA BIOS path and filename" # string "VGA BIOS path and filename"
@ -129,14 +129,13 @@ config VGA_BIOS
# default "rom/video/OntarioGenericVBios.bin" # default "rom/video/OntarioGenericVBios.bin"
config VGA_BIOS_ID config VGA_BIOS_ID
string "VGA device PCI IDs" string "VGA device PCI IDs"
depends on VGA_BIOS depends on VGA_BIOS
default "1002,9802" default "1002,9802"
config SB800_AHCI_ROM config SB800_AHCI_ROM
bool bool
default n default n
endif # BOARD_AMD_INAGUA endif # BOARD_AMD_INAGUA

174
src/mainboard/amd/inagua/PlatformGnbPcie.c
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@ -44,8 +44,8 @@
/*---------------------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------------------*/
VOID VOID
OemCustomizeInitEarly ( OemCustomizeInitEarly (
IN OUT AMD_EARLY_PARAMS *InitEarly IN OUT AMD_EARLY_PARAMS *InitEarly
) )
{ {
AGESA_STATUS Status; AGESA_STATUS Status;
VOID *BrazosPcieComplexListPtr; VOID *BrazosPcieComplexListPtr;
@ -54,105 +54,105 @@ OemCustomizeInitEarly (
ALLOCATE_HEAP_PARAMS AllocHeapParams; ALLOCATE_HEAP_PARAMS AllocHeapParams;
PCIe_PORT_DESCRIPTOR PortList [] = { PCIe_PORT_DESCRIPTOR PortList [] = {
// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) MXM // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) MXM
{ {
0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 5), PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 5),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4) PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4)
}, },
// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) PCIE LAN // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) PCIE LAN
{ {
0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6) PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6)
}, },
// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) MINIPCIE SLOT1 // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) MINIPCIE SLOT1
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7) PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7)
}, },
// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
{ {
DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
} }
}; };
PCIe_DDI_DESCRIPTOR DdiList [] = { PCIe_DDI_DESCRIPTOR DdiList [] = {
// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) DP0 to LVDS // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) DP0 to LVDS
{ {
0, //Descriptor flags 0, //Descriptor flags
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeLvds, Aux1, Hdp1) PCIE_DDI_DATA_INITIALIZER (ConnectorTypeLvds, Aux1, Hdp1)
}, },
// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) DP1 to VGA // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) DP1 to VGA
{ {
DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeAutoDetect, Aux2, Hdp2) PCIE_DDI_DATA_INITIALIZER (ConnectorTypeAutoDetect, Aux2, Hdp2)
} }
}; };
PCIe_COMPLEX_DESCRIPTOR Brazos = { PCIe_COMPLEX_DESCRIPTOR Brazos = {
DESCRIPTOR_TERMINATE_LIST, DESCRIPTOR_TERMINATE_LIST,
0, 0,
&PortList[0], &PortList[0],
&DdiList[0] &DdiList[0]
}; };
// GNB PCIe topology Porting // GNB PCIe topology Porting
// //
// Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
// //
AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) + AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) +
sizeof (PCIe_PORT_DESCRIPTOR) * 5 + sizeof (PCIe_PORT_DESCRIPTOR) * 5 +
sizeof (PCIe_DDI_DESCRIPTOR)) * 2; sizeof (PCIe_DDI_DESCRIPTOR)) * 2;
AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
AllocHeapParams.Persist = HEAP_LOCAL_CACHE; AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
if ( Status!= AGESA_SUCCESS) { if ( Status!= AGESA_SUCCESS) {
// Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
ASSERT(FALSE); ASSERT(FALSE);
return; return;
} }
BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR); AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR);
BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5; AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5;
BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
LibAmdMemFill (BrazosPcieComplexListPtr, LibAmdMemFill (BrazosPcieComplexListPtr,
0, 0,
sizeof (PCIe_COMPLEX_DESCRIPTOR), sizeof (PCIe_COMPLEX_DESCRIPTOR),
&InitEarly->StdHeader); &InitEarly->StdHeader);
LibAmdMemFill (BrazosPciePortPtr, LibAmdMemFill (BrazosPciePortPtr,
0, 0,
sizeof (PCIe_PORT_DESCRIPTOR) * 5, sizeof (PCIe_PORT_DESCRIPTOR) * 5,
&InitEarly->StdHeader); &InitEarly->StdHeader);
LibAmdMemFill (BrazosPcieDdiPtr, LibAmdMemFill (BrazosPcieDdiPtr,
0, 0,
sizeof (PCIe_DDI_DESCRIPTOR) * 2, sizeof (PCIe_DDI_DESCRIPTOR) * 2,
&InitEarly->StdHeader); &InitEarly->StdHeader);
LibAmdMemCopy (BrazosPcieComplexListPtr, &Brazos, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader); LibAmdMemCopy (BrazosPcieComplexListPtr, &Brazos, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader);
LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 5, &InitEarly->StdHeader); LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 5, &InitEarly->StdHeader);
LibAmdMemCopy (BrazosPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) *2, &InitEarly->StdHeader); LibAmdMemCopy (BrazosPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) *2, &InitEarly->StdHeader);
((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr; ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
InitEarly->GnbConfig.PsppPolicy = 0; InitEarly->GnbConfig.PsppPolicy = 0;
} }

15
src/mainboard/amd/inagua/PlatformGnbPcieComplex.h
View File

@ -29,7 +29,7 @@
#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 #define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) #define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced #define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port5 //GNB GPP Port5
@ -37,7 +37,7 @@
#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 #define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) #define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced #define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port6 //GNB GPP Port6
@ -45,7 +45,7 @@
#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 #define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) #define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced #define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port7 //GNB GPP Port7
@ -53,7 +53,7 @@
#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 #define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) #define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced #define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port8 //GNB GPP Port8
@ -61,12 +61,9 @@
#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 #define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) #define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced #define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
VOID VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly);
OemCustomizeInitEarly (
IN OUT AMD_EARLY_PARAMS *InitEarly
);
#endif //_PLATFORM_GNB_PCIE_COMPLEX_H #endif //_PLATFORM_GNB_PCIE_COMPLEX_H

2
src/mainboard/amd/inagua/acpi_tables.c
View File

@ -86,7 +86,7 @@ unsigned long acpi_fill_madt(unsigned long current)
/* Write SB800 IOAPIC, only one */ /* Write SB800 IOAPIC, only one */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); CONFIG_MAX_CPUS, IO_APIC_ADDR, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
current, 0, 0, 2, 0); current, 0, 0, 2, 0);

148
src/mainboard/amd/inagua/agesawrapper.c
View File

@ -78,8 +78,8 @@ VOID *AcpiAlib = NULL;
*/ */
UINT32 UINT32
agesawrapper_amdinitcpuio ( agesawrapper_amdinitcpuio (
VOID VOID
) )
{ {
AGESA_STATUS Status; AGESA_STATUS Status;
UINT64 MsrReg; UINT64 MsrReg;
@ -127,8 +127,8 @@ agesawrapper_amdinitcpuio (
UINT32 UINT32
agesawrapper_amdinitmmio ( agesawrapper_amdinitmmio (
VOID VOID
) )
{ {
AGESA_STATUS Status; AGESA_STATUS Status;
UINT64 MsrReg; UINT64 MsrReg;
@ -141,9 +141,9 @@ agesawrapper_amdinitmmio (
UINT8 Index; UINT8 Index;
/* /*
Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
Address MSR register. Address MSR register.
*/ */
for (Index = 0; Index < 8; Index++) { for (Index = 0; Index < 8; Index++) {
BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index; BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index;
@ -157,8 +157,8 @@ agesawrapper_amdinitmmio (
LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
/* /*
Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
*/ */
LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
MsrReg = MsrReg | 0x0000400000000000ull; MsrReg = MsrReg | 0x0000400000000000ull;
LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
@ -177,22 +177,22 @@ agesawrapper_amdinitmmio (
UINT32 UINT32
agesawrapper_amdinitreset ( agesawrapper_amdinitreset (
VOID VOID
) )
{ {
AGESA_STATUS status; AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct; AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_RESET_PARAMS AmdResetParams; AMD_RESET_PARAMS AmdResetParams;
LibAmdMemFill (&AmdParamStruct, LibAmdMemFill (&AmdParamStruct,
0, 0,
sizeof (AMD_INTERFACE_PARAMS), sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader)); &(AmdParamStruct.StdHeader));
LibAmdMemFill (&AmdResetParams, LibAmdMemFill (&AmdResetParams,
0, 0,
sizeof (AMD_RESET_PARAMS), sizeof (AMD_RESET_PARAMS),
&(AmdResetParams.StdHeader)); &(AmdResetParams.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
AmdParamStruct.AllocationMethod = ByHost; AmdParamStruct.AllocationMethod = ByHost;
@ -209,21 +209,21 @@ agesawrapper_amdinitreset (
if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
AmdReleaseStruct (&AmdParamStruct); AmdReleaseStruct (&AmdParamStruct);
return (UINT32)status; return (UINT32)status;
} }
UINT32 UINT32
agesawrapper_amdinitearly ( agesawrapper_amdinitearly (
VOID VOID
) )
{ {
AGESA_STATUS status; AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct; AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_EARLY_PARAMS *AmdEarlyParamsPtr; AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
LibAmdMemFill (&AmdParamStruct, LibAmdMemFill (&AmdParamStruct,
0, 0,
sizeof (AMD_INTERFACE_PARAMS), sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader)); &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
AmdParamStruct.AllocationMethod = PreMemHeap; AmdParamStruct.AllocationMethod = PreMemHeap;
@ -245,8 +245,8 @@ agesawrapper_amdinitearly (
UINT32 UINT32
agesawrapper_amdinitpost ( agesawrapper_amdinitpost (
VOID VOID
) )
{ {
AGESA_STATUS status; AGESA_STATUS status;
UINT16 i; UINT16 i;
@ -255,9 +255,9 @@ agesawrapper_amdinitpost (
BIOS_HEAP_MANAGER *BiosManagerPtr; BIOS_HEAP_MANAGER *BiosManagerPtr;
LibAmdMemFill (&AmdParamStruct, LibAmdMemFill (&AmdParamStruct,
0, 0,
sizeof (AMD_INTERFACE_PARAMS), sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader)); &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
AmdParamStruct.AllocationMethod = PreMemHeap; AmdParamStruct.AllocationMethod = PreMemHeap;
@ -287,8 +287,8 @@ agesawrapper_amdinitpost (
UINT32 UINT32
agesawrapper_amdinitenv ( agesawrapper_amdinitenv (
VOID VOID
) )
{ {
AGESA_STATUS status; AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct; AMD_INTERFACE_PARAMS AmdParamStruct;
@ -296,9 +296,9 @@ agesawrapper_amdinitenv (
UINT32 PciValue; UINT32 PciValue;
LibAmdMemFill (&AmdParamStruct, LibAmdMemFill (&AmdParamStruct,
0, 0,
sizeof (AMD_INTERFACE_PARAMS), sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader)); &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
AmdParamStruct.AllocationMethod = PostMemDram; AmdParamStruct.AllocationMethod = PostMemDram;
@ -311,7 +311,7 @@ agesawrapper_amdinitenv (
if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
/* Initialize Subordinate Bus Number and Secondary Bus Number /* Initialize Subordinate Bus Number and Secondary Bus Number
* In platform BIOS this address is allocated by PCI enumeration code * In platform BIOS this address is allocated by PCI enumeration code
Modify D1F0x18 Modify D1F0x18
*/ */
PciAddress.Address.Bus = 0; PciAddress.Address.Bus = 0;
PciAddress.Address.Device = 1; PciAddress.Address.Device = 1;
@ -323,8 +323,8 @@ agesawrapper_amdinitenv (
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize GMM Base Address for Legacy Bridge Mode /* Initialize GMM Base Address for Legacy Bridge Mode
* Modify B1D5F0x18 * Modify B1D5F0x18
*/ */
PciAddress.Address.Bus = 1; PciAddress.Address.Bus = 1;
PciAddress.Address.Device = 5; PciAddress.Address.Device = 5;
PciAddress.Address.Function = 0; PciAddress.Address.Function = 0;
@ -335,16 +335,16 @@ agesawrapper_amdinitenv (
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize FB Base Address for Legacy Bridge Mode /* Initialize FB Base Address for Legacy Bridge Mode
* Modify B1D5F0x10 * Modify B1D5F0x10
*/ */
PciAddress.Address.Register = 0x10; PciAddress.Address.Register = 0x10;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x80000000; PciValue |= 0x80000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize GMM Base Address for Pcie Mode /* Initialize GMM Base Address for Pcie Mode
* Modify B0D1F0x18 * Modify B0D1F0x18
*/ */
PciAddress.Address.Bus = 0; PciAddress.Address.Bus = 0;
PciAddress.Address.Device = 1; PciAddress.Address.Device = 1;
PciAddress.Address.Function = 0; PciAddress.Address.Function = 0;
@ -355,16 +355,16 @@ agesawrapper_amdinitenv (
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize FB Base Address for Pcie Mode /* Initialize FB Base Address for Pcie Mode
* Modify B0D1F0x10 * Modify B0D1F0x10
*/ */
PciAddress.Address.Register = 0x10; PciAddress.Address.Register = 0x10;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x80000000; PciValue |= 0x80000000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize MMIO Base and Limit Address /* Initialize MMIO Base and Limit Address
* Modify B0D1F0x20 * Modify B0D1F0x20
*/ */
PciAddress.Address.Bus = 0; PciAddress.Address.Bus = 0;
PciAddress.Address.Device = 1; PciAddress.Address.Device = 1;
PciAddress.Address.Function = 0; PciAddress.Address.Function = 0;
@ -375,8 +375,8 @@ agesawrapper_amdinitenv (
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
/* Initialize MMIO Prefetchable Memory Limit and Base /* Initialize MMIO Prefetchable Memory Limit and Base
* Modify B0D1F0x24 * Modify B0D1F0x24
*/ */
PciAddress.Address.Register = 0x24; PciAddress.Address.Register = 0x24;
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
PciValue |= 0x8FF18001; PciValue |= 0x8FF18001;
@ -388,8 +388,8 @@ agesawrapper_amdinitenv (
VOID * VOID *
agesawrapper_getlateinitptr ( agesawrapper_getlateinitptr (
int pick int pick
) )
{ {
switch (pick) { switch (pick) {
case PICK_DMI: case PICK_DMI:
@ -413,8 +413,8 @@ agesawrapper_getlateinitptr (
UINT32 UINT32
agesawrapper_amdinitmid ( agesawrapper_amdinitmid (
VOID VOID
) )
{ {
AGESA_STATUS status; AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct; AMD_INTERFACE_PARAMS AmdParamStruct;
@ -423,9 +423,9 @@ agesawrapper_amdinitmid (
agesawrapper_amdinitcpuio (); agesawrapper_amdinitcpuio ();
LibAmdMemFill (&AmdParamStruct, LibAmdMemFill (&AmdParamStruct,
0, 0,
sizeof (AMD_INTERFACE_PARAMS), sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader)); &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
AmdParamStruct.AllocationMethod = PostMemDram; AmdParamStruct.AllocationMethod = PostMemDram;
@ -445,17 +445,17 @@ agesawrapper_amdinitmid (
UINT32 UINT32
agesawrapper_amdinitlate ( agesawrapper_amdinitlate (
VOID VOID
) )
{ {
AGESA_STATUS Status; AGESA_STATUS Status;
AMD_INTERFACE_PARAMS AmdParamStruct; AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_LATE_PARAMS * AmdLateParamsPtr; AMD_LATE_PARAMS * AmdLateParamsPtr;
LibAmdMemFill (&AmdParamStruct, LibAmdMemFill (&AmdParamStruct,
0, 0,
sizeof (AMD_INTERFACE_PARAMS), sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader)); &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
AmdParamStruct.AllocationMethod = PostMemDram; AmdParamStruct.AllocationMethod = PostMemDram;
@ -484,10 +484,10 @@ agesawrapper_amdinitlate (
AcpiAlib = AmdLateParamsPtr->AcpiAlib; AcpiAlib = AmdLateParamsPtr->AcpiAlib;
printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n" printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n"
" DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n" " DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n"
" Mce:%p\n Cmc:%p\n Alib:%p\n", " Mce:%p\n Cmc:%p\n Alib:%p\n",
__func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit, __func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit,
AcpiWheaMce, AcpiWheaCmc, AcpiAlib); AcpiWheaMce, AcpiWheaCmc, AcpiAlib);
/* Don't release the structure until coreboot has copied the ACPI tables. /* Don't release the structure until coreboot has copied the ACPI tables.
* AmdReleaseStruct (&AmdLateParams); * AmdReleaseStruct (&AmdLateParams);
@ -498,18 +498,18 @@ agesawrapper_amdinitlate (
UINT32 UINT32
agesawrapper_amdlaterunaptask ( agesawrapper_amdlaterunaptask (
UINT32 Func, UINT32 Func,
UINT32 Data, UINT32 Data,
VOID *ConfigPtr VOID *ConfigPtr
) )
{ {
AGESA_STATUS Status; AGESA_STATUS Status;
AP_EXE_PARAMS ApExeParams; AP_EXE_PARAMS ApExeParams;
LibAmdMemFill (&ApExeParams, LibAmdMemFill (&ApExeParams,
0, 0,
sizeof (AP_EXE_PARAMS), sizeof (AP_EXE_PARAMS),
&(ApExeParams.StdHeader)); &(ApExeParams.StdHeader));
ApExeParams.StdHeader.AltImageBasePtr = 0; ApExeParams.StdHeader.AltImageBasePtr = 0;
ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
@ -529,16 +529,16 @@ agesawrapper_amdlaterunaptask (
UINT32 UINT32
agesawrapper_amdreadeventlog ( agesawrapper_amdreadeventlog (
VOID VOID
) )
{ {
AGESA_STATUS Status; AGESA_STATUS Status;
EVENT_PARAMS AmdEventParams; EVENT_PARAMS AmdEventParams;
LibAmdMemFill (&AmdEventParams, LibAmdMemFill (&AmdEventParams,
0, 0,
sizeof (EVENT_PARAMS), sizeof (EVENT_PARAMS),
&(AmdEventParams.StdHeader)); &(AmdEventParams.StdHeader));
AmdEventParams.StdHeader.AltImageBasePtr = 0; AmdEventParams.StdHeader.AltImageBasePtr = 0;
AmdEventParams.StdHeader.CalloutPtr = NULL; AmdEventParams.StdHeader.CalloutPtr = NULL;

18
src/mainboard/amd/inagua/agesawrapper.h
View File

@ -39,13 +39,13 @@
#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS #define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
enum { enum {
PICK_DMI, /* DMI Interface */ PICK_DMI, /* DMI Interface */
PICK_PSTATE, /* Acpi Pstate SSDT Table */ PICK_PSTATE, /* Acpi Pstate SSDT Table */
PICK_SRAT, /* SRAT Table */ PICK_SRAT, /* SRAT Table */
PICK_SLIT, /* SLIT Table */ PICK_SLIT, /* SLIT Table */
PICK_WHEA_MCE, /* WHEA MCE table */ PICK_WHEA_MCE, /* WHEA MCE table */
PICK_WHEA_CMC, /* WHEA CMV table */ PICK_WHEA_CMC, /* WHEA CMV table */
PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ PICK_ALIB, /* SACPI SSDT table with ALIB implementation */
}; };
/*---------------------------------------------------------------------------------------- /*----------------------------------------------------------------------------------------
@ -54,8 +54,8 @@ enum {
*/ */
typedef struct { typedef struct {
UINT32 CalloutName; UINT32 CalloutName;
AGESA_STATUS (*CalloutPtr) (UINT32 Func, UINT32 Data, VOID* ConfigPtr); AGESA_STATUS (*CalloutPtr) (UINT32 Func, UINT32 Data, VOID* ConfigPtr);
} BIOS_CALLOUT_STRUCT; } BIOS_CALLOUT_STRUCT;
/*---------------------------------------------------------------------------------------- /*----------------------------------------------------------------------------------------

200
src/mainboard/amd/inagua/buildOpts.c
View File

@ -89,12 +89,12 @@
#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE #define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
#define BLDOPT_REMOVE_ACPI_PSTATES FALSE #define BLDOPT_REMOVE_ACPI_PSTATES FALSE
#define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE
#define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE
#define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE #define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE
#define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE
#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE
#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE
#define BLDOPT_REMOVE_SRAT FALSE #define BLDOPT_REMOVE_SRAT FALSE
#define BLDOPT_REMOVE_SLIT FALSE #define BLDOPT_REMOVE_SLIT FALSE
#define BLDOPT_REMOVE_WHEA FALSE #define BLDOPT_REMOVE_WHEA FALSE
@ -329,65 +329,65 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
* use its default conservative settings. * use its default conservative settings.
*/ */
CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
// //
// The following macros are supported (use comma to separate macros): // The following macros are supported (use comma to separate macros):
// //
// MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
// The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
// AGESA will base on this value to disable unused MemClk to save power. // AGESA will base on this value to disable unused MemClk to save power.
// Example: // Example:
// BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
// Bit AM3/S1g3 pin name // Bit AM3/S1g3 pin name
// 0 M[B,A]_CLK_H/L[0] // 0 M[B,A]_CLK_H/L[0]
// 1 M[B,A]_CLK_H/L[1] // 1 M[B,A]_CLK_H/L[1]
// 2 M[B,A]_CLK_H/L[2] // 2 M[B,A]_CLK_H/L[2]
// 3 M[B,A]_CLK_H/L[3] // 3 M[B,A]_CLK_H/L[3]
// 4 M[B,A]_CLK_H/L[4] // 4 M[B,A]_CLK_H/L[4]
// 5 M[B,A]_CLK_H/L[5] // 5 M[B,A]_CLK_H/L[5]
// 6 M[B,A]_CLK_H/L[6] // 6 M[B,A]_CLK_H/L[6]
// 7 M[B,A]_CLK_H/L[7] // 7 M[B,A]_CLK_H/L[7]
// And platform has the following routing: // And platform has the following routing:
// CS0 M[B,A]_CLK_H/L[4] // CS0 M[B,A]_CLK_H/L[4]
// CS1 M[B,A]_CLK_H/L[2] // CS1 M[B,A]_CLK_H/L[2]
// CS2 M[B,A]_CLK_H/L[3] // CS2 M[B,A]_CLK_H/L[3]
// CS3 M[B,A]_CLK_H/L[5] // CS3 M[B,A]_CLK_H/L[5]
// Then platform can specify the following macro: // Then platform can specify the following macro:
// MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
// //
// CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
// The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
// AGESA will base on this value to tristate unused CKE to save power. // AGESA will base on this value to tristate unused CKE to save power.
// //
// ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
// The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
// AGESA will base on this value to tristate unused ODT pins to save power. // AGESA will base on this value to tristate unused ODT pins to save power.
// //
// CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
// The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
// AGESA will base on this value to tristate unused Chip select to save power. // AGESA will base on this value to tristate unused Chip select to save power.
// //
// NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
// Specifies the number of DIMM slots per channel. // Specifies the number of DIMM slots per channel.
// //
// NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
// Specifies the number of Chip selects per channel. // Specifies the number of Chip selects per channel.
// //
// NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
// Specifies the number of channels per socket. // Specifies the number of channels per socket.
// //
// OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED) // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
// Specifies DDR bus speed of channel ChannelID on socket SocketID. // Specifies DDR bus speed of channel ChannelID on socket SocketID.
// //
// DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE) // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
// Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
// //
// WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
// Byte6Seed, Byte7Seed, ByteEccSeed) // Byte6Seed, Byte7Seed, ByteEccSeed)
// Specifies the write leveling seed for a channel of a socket. // Specifies the write leveling seed for a channel of a socket.
// //
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
PSO_END PSO_END
}; };
/* /*
@ -399,45 +399,45 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
//DA Customer table //DA Customer table
CONST UINT8 AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] = CONST UINT8 AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] =
{ {
// Hardcoded Memory Training Values // Hardcoded Memory Training Values
// The following macro should be used to override training values for your platform // The following macro should be used to override training values for your platform
// //
// DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20), // DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20),
// //
// NOTE: // NOTE:
// The following training hardcode values are example values that were taken from a tilapia motherboard // The following training hardcode values are example values that were taken from a tilapia motherboard
// with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in // with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in
// the table and replace the byte lane values with your own. // the table and replace the byte lane values with your own.
// //
// ------------------ BYTE LANES ---------------------- // ------------------ BYTE LANES ----------------------
// BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC
// Write Data Timing // Write Data Timing
// DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0 // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0
// DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1 // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1
// DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x27, 0x2B, 0x3B, 0x3B, 0x3E, 0x3E, 0x30),// DCT1, DIMM0 // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x27, 0x2B, 0x3B, 0x3B, 0x3E, 0x3E, 0x30),// DCT1, DIMM0
// DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1 // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1
// DQS Receiver Enable // DQS Receiver Enable
// DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0
// DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1 // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1
// DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT1, DIMM0 // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT1, DIMM0
// DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1 // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1
// Write DQS Delays // Write DQS Delays
// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0
// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1 // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1
// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x07, 0x0E, 0x14, 0x1B, 0x24, 0x29, 0x2B, 0x2C, 0x1F),// DCT1, DIMM0 // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x07, 0x0E, 0x14, 0x1B, 0x24, 0x29, 0x2B, 0x2C, 0x1F),// DCT1, DIMM0
// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1 // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1
// Read DQS Delays // Read DQS Delays
// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x10),// DCT0, DIMM0 // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x10),// DCT0, DIMM0
// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1 // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1
// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM0 // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM0
// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1 // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1
//-------------------------------------------------------------------------------------------------------------------------------------------------- //--------------------------------------------------------------------------------------------------------------------------------------------------
// TABLE END // TABLE END
NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table
}; };
CONST UINT8 SizeOfTableON = sizeof (AGESA_MEM_TABLE_ON) / sizeof (AGESA_MEM_TABLE_ON[0]); CONST UINT8 SizeOfTableON = sizeof (AGESA_MEM_TABLE_ON) / sizeof (AGESA_MEM_TABLE_ON[0]);

120
src/mainboard/amd/inagua/devicetree.cb
View File

@ -17,56 +17,56 @@
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
# #
chip northbridge/amd/agesa/family14/root_complex chip northbridge/amd/agesa/family14/root_complex
device lapic_cluster 0 on device lapic_cluster 0 on
chip cpu/amd/agesa/family14 chip cpu/amd/agesa/family14
device lapic 0 on end device lapic 0 on end
end end
end end
device pci_domain 0 on device pci_domain 0 on
subsystemid 0x1022 0x1510 inherit subsystemid 0x1022 0x1510 inherit
chip northbridge/amd/agesa/family14 # CPU side of HT root complex chip northbridge/amd/agesa/family14 # CPU side of HT root complex
# device pci 18.0 on # northbridge # device pci 18.0 on # northbridge
chip northbridge/amd/agesa/family14 # PCI side of HT root complex chip northbridge/amd/agesa/family14 # PCI side of HT root complex
device pci 0.0 on end # Root Complex device pci 0.0 on end # Root Complex
device pci 1.0 on end # Internal Graphics P2P bridge, 9802 to 9806 device pci 1.0 on end # Internal Graphics P2P bridge, 9802 to 9806
device pci 1.1 on end # Internal Multimedia device pci 1.1 on end # Internal Multimedia
device pci 4.0 on end # PCIE P2P bridge MXM lane 0 device pci 4.0 on end # PCIE P2P bridge MXM lane 0
device pci 5.0 off end # PCIE P2P bridge MXM lane 1 device pci 5.0 off end # PCIE P2P bridge MXM lane 1
device pci 6.0 on end # PCIE P2P bridge LAN device pci 6.0 on end # PCIE P2P bridge LAN
device pci 7.0 on end # PCIE P2P bridge MINIPCIE SLOT1 device pci 7.0 on end # PCIE P2P bridge MINIPCIE SLOT1
device pci 8.0 off end # NB/SB Link P2P bridge device pci 8.0 off end # NB/SB Link P2P bridge
end # agesa northbridge end # agesa northbridge
chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus
device pci 11.0 on end # SATA device pci 11.0 on end # SATA
device pci 12.0 on end # USB device pci 12.0 on end # USB
device pci 12.1 on end # USB device pci 12.1 on end # USB
device pci 12.2 on end # USB device pci 12.2 on end # USB
device pci 13.0 on end # USB device pci 13.0 on end # USB
device pci 13.1 on end # USB device pci 13.1 on end # USB
device pci 13.2 on end # USB device pci 13.2 on end # USB
device pci 14.0 on # SM device pci 14.0 on # SM
chip drivers/generic/generic #dimm 0-0-0 chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end device i2c 50 on end
end end
chip drivers/generic/generic #dimm 0-0-1 chip drivers/generic/generic #dimm 0-0-1
device i2c 51 on end device i2c 51 on end
end end
end # SM end # SM
device pci 14.1 on end # IDE 0x439c device pci 14.1 on end # IDE 0x439c
device pci 14.2 on end # HDA 0x4383 device pci 14.2 on end # HDA 0x4383
device pci 14.3 on # LPC 0x439d device pci 14.3 on # LPC 0x439d
chip superio/smsc/kbc1100 chip superio/smsc/kbc1100
device pnp 2e.7 on # Keyboard device pnp 2e.7 on # Keyboard
io 0x60 = 0x60 io 0x60 = 0x60
io 0x62 = 0x64 io 0x62 = 0x64
irq 0x70 = 1 irq 0x70 = 1
irq 0x72 = 12 irq 0x72 = 12
end end
end # kbc1100 end # kbc1100
end #LPC end #LPC
device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
device pci 14.5 on end # USB 2 device pci 14.5 on end # USB 2
device pci 15.0 on end # PCIe PortA Express Card device pci 15.0 on end # PCIe PortA Express Card
device pci 15.1 on end # PCIe PortB NEC USB3.0 device pci 15.1 on end # PCIe PortB NEC USB3.0
device pci 15.2 on end # PCIe PortC MINIPCIE SLOT2 device pci 15.2 on end # PCIe PortC MINIPCIE SLOT2
@ -74,20 +74,20 @@ chip northbridge/amd/agesa/family14/root_complex
device pci 16.0 on end # OHCI USB3 device pci 16.0 on end # OHCI USB3
device pci 16.2 on end # EHCI USB3 device pci 16.2 on end # EHCI USB3
register "gpp_configuration" = "4" #1:1:1:1 register "gpp_configuration" = "4" #1:1:1:1
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
end #southbridge/amd/cimx/sb800 end #southbridge/amd/cimx/sb800
# end # device pci 18.0 # end # device pci 18.0
# These seem unnecessary # These seem unnecessary
device pci 18.0 on end device pci 18.0 on end
#device pci 18.0 on end #device pci 18.0 on end
device pci 18.1 on end device pci 18.1 on end
device pci 18.2 on end device pci 18.2 on end
device pci 18.3 on end device pci 18.3 on end
device pci 18.4 on end device pci 18.4 on end
device pci 18.5 on end device pci 18.5 on end
device pci 18.6 on end device pci 18.6 on end
device pci 18.7 on end device pci 18.7 on end
end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
end #pci_domain end #pci_domain
end #northbridge/amd/agesa/family14/root_complex end #northbridge/amd/agesa/family14/root_complex

142
src/mainboard/amd/inagua/dimmSpd.c
View File

@ -26,19 +26,19 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA
#define DIMENSION(array)(sizeof (array)/ sizeof (array [0])) #define DIMENSION(array)(sizeof (array)/ sizeof (array [0]))
/*#pragma optimize ("", off) // for source level debug /*#pragma optimize ("", off) // for source level debug
*--------------------------------------------------------------------------- *---------------------------------------------------------------------------
* *
* SPD address table - porting required * SPD address table - porting required
*/ */
static const UINT8 spdAddressLookup [1] [2] [2] = // socket, channel, dimm static const UINT8 spdAddressLookup [1] [2] [2] = // socket, channel, dimm
{ {
// socket 0 // socket 0
{ {
{0xA0, 0xA2}, // channel 0 dimms {0xA0, 0xA2}, // channel 0 dimms
{0x00, 0x00}, // channel 1 dimms {0x00, 0x00}, // channel 1 dimms
}, },
}; };
/*----------------------------------------------------------------------------- /*-----------------------------------------------------------------------------
* *
@ -47,30 +47,30 @@ static const UINT8 spdAddressLookup [1] [2] [2] = // socket, channel, dimm
static int readSmbusByteData (int iobase, int address, char *buffer, int offset) static int readSmbusByteData (int iobase, int address, char *buffer, int offset)
{ {
unsigned int status; unsigned int status;
UINT64 limit; UINT64 limit;
address |= 1; // set read bit address |= 1; // set read bit
__outbyte (iobase + 0, 0xFF); // clear error status __outbyte (iobase + 0, 0xFF); // clear error status
__outbyte (iobase + 1, 0x1F); // clear error status __outbyte (iobase + 1, 0x1F); // clear error status
__outbyte (iobase + 3, offset); // offset in eeprom __outbyte (iobase + 3, offset); // offset in eeprom
__outbyte (iobase + 4, address); // slave address and read bit __outbyte (iobase + 4, address); // slave address and read bit
__outbyte (iobase + 2, 0x48); // read byte command __outbyte (iobase + 2, 0x48); // read byte command
// time limit to avoid hanging for unexpected error status (should never happen) // time limit to avoid hanging for unexpected error status (should never happen)
limit = __rdtsc () + 2000000000 / 10; limit = __rdtsc () + 2000000000 / 10;
for (;;) { for (;;) {
status = __inbyte (iobase); status = __inbyte (iobase);
if (__rdtsc () > limit) break; if (__rdtsc () > limit) break;
if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting
if ((status & 1) == 1) continue; // HostBusy set, keep waiting if ((status & 1) == 1) continue; // HostBusy set, keep waiting
break; break;
} }
buffer [0] = __inbyte (iobase + 5); buffer [0] = __inbyte (iobase + 5);
if (status == 2) status = 0; // check for done with no errors if (status == 2) status = 0; // check for done with no errors
return status; return status;
} }
/*----------------------------------------------------------------------------- /*-----------------------------------------------------------------------------
@ -81,25 +81,25 @@ static int readSmbusByteData (int iobase, int address, char *buffer, int offset)
static int readSmbusByte (int iobase, int address, char *buffer) static int readSmbusByte (int iobase, int address, char *buffer)
{ {
unsigned int status; unsigned int status;
UINT64 limit; UINT64 limit;
__outbyte (iobase + 0, 0xFF); // clear error status __outbyte (iobase + 0, 0xFF); // clear error status
__outbyte (iobase + 2, 0x44); // read command __outbyte (iobase + 2, 0x44); // read command
// time limit to avoid hanging for unexpected error status // time limit to avoid hanging for unexpected error status
limit = __rdtsc () + 2000000000 / 10; limit = __rdtsc () + 2000000000 / 10;
for (;;) { for (;;) {
status = __inbyte (iobase); status = __inbyte (iobase);
if (__rdtsc () > limit) break; if (__rdtsc () > limit) break;
if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting
if ((status & 1) == 1) continue; // HostBusy set, keep waiting if ((status & 1) == 1) continue; // HostBusy set, keep waiting
break; break;
} }
buffer [0] = __inbyte (iobase + 5); buffer [0] = __inbyte (iobase + 5);
if (status == 2) status = 0; // check for done with no errors if (status == 2) status = 0; // check for done with no errors
return status; return status;
} }
/*--------------------------------------------------------------------------- /*---------------------------------------------------------------------------
@ -113,47 +113,47 @@ static int readSmbusByte (int iobase, int address, char *buffer)
static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count) static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count)
{ {
int index, error; int index, error;
/* read the first byte using offset zero */ /* read the first byte using offset zero */
error = readSmbusByteData (iobase, SmbusSlaveAddress, buffer, 0); error = readSmbusByteData (iobase, SmbusSlaveAddress, buffer, 0);
if (error) return error; if (error) return error;
/* read the remaining bytes using auto-increment for speed */ /* read the remaining bytes using auto-increment for speed */
for (index = 1; index < count; index++) { for (index = 1; index < count; index++) {
error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]); error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]);
if (error) return error; if (error) return error;
} }
return 0; return 0;
} }
static void writePmReg (int reg, int data) static void writePmReg (int reg, int data)
{ {
__outbyte (0xCD6, reg); __outbyte (0xCD6, reg);
__outbyte (0xCD7, data); __outbyte (0xCD7, data);
} }
static void setupFch (int ioBase) static void setupFch (int ioBase)
{ {
writePmReg (0x2D, ioBase >> 8); writePmReg (0x2D, ioBase >> 8);
writePmReg (0x2C, ioBase | 1); writePmReg (0x2C, ioBase | 1);
writePmReg (0x29, 0x80); writePmReg (0x29, 0x80);
writePmReg (0x28, 0x61); writePmReg (0x28, 0x61);
__outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz
} }
AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info) AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info)
{ {
int spdAddress, ioBase; int spdAddress, ioBase;
if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR; if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR;
if (info->MemChannelId >= DIMENSION (spdAddressLookup[0] )) return AGESA_ERROR; if (info->MemChannelId >= DIMENSION (spdAddressLookup[0] )) return AGESA_ERROR;
if (info->DimmId >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR; if (info->DimmId >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR;
spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId];
if (spdAddress == 0) return AGESA_ERROR; if (spdAddress == 0) return AGESA_ERROR;
ioBase = SMBUS0_BASE_ADDRESS; ioBase = SMBUS0_BASE_ADDRESS;
setupFch (ioBase); setupFch (ioBase);
return readspd (ioBase, spdAddress, (void *) info->Buffer, 128); return readspd (ioBase, spdAddress, (void *) info->Buffer, 128);
} }

128
src/mainboard/amd/inagua/get_bus_conf.c
View File

@ -31,19 +31,19 @@
/* Global variables for MB layouts and these will be shared by irqtable mptable /* Global variables for MB layouts and these will be shared by irqtable mptable
* and acpi_tables busnum is default. * and acpi_tables busnum is default.
*/ */
u8 bus_isa; u8 bus_isa;
u8 bus_sb800[3]; u8 bus_sb800[3];
u32 apicid_sb800; u32 apicid_sb800;
/* /*
* Here you only need to set value in pci1234 for HT-IO that could be installed or not * Here you only need to set value in pci1234 for HT-IO that could be installed or not
* You may need to preset pci1234 for HTIO board, * You may need to preset pci1234 for HTIO board,
* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
*/ */
u32 pci1234x[] = { u32 pci1234x[] = {
0x0000ff0, 0x0000ff0,
}; };
u32 bus_type[256]; u32 bus_type[256];
@ -55,81 +55,81 @@ static u32 get_bus_conf_done = 0;
void get_bus_conf(void) void get_bus_conf(void)
{ {
u32 apicid_base; u32 apicid_base;
u32 status; u32 status;
device_t dev; device_t dev;
int i, j; int i, j;
if (get_bus_conf_done == 1) if (get_bus_conf_done == 1)
return; /* do it only once */ return; /* do it only once */
get_bus_conf_done = 1; get_bus_conf_done = 1;
/* /*
* This is the call to AmdInitLate. It is really in the wrong place, conceptually, * This is the call to AmdInitLate. It is really in the wrong place, conceptually,
* but functionally within the coreboot model, this is the best place to make the * but functionally within the coreboot model, this is the best place to make the
* call. The logically correct place to call AmdInitLate is after PCI scan is done, * call. The logically correct place to call AmdInitLate is after PCI scan is done,
* after the decision about S3 resume is made, and before the system tables are * after the decision about S3 resume is made, and before the system tables are
* written into RAM. The routine that is responsible for writing the tables is * written into RAM. The routine that is responsible for writing the tables is
* "write_tables", called near the end of "hardwaremain". There is no platform * "write_tables", called near the end of "hardwaremain". There is no platform
* specific entry point between the S3 resume decision point and the call to * specific entry point between the S3 resume decision point and the call to
* "write_tables", and the next platform specific entry points are the calls to * "write_tables", and the next platform specific entry points are the calls to
* the ACPI table write functions. The first of ose would seem to be the right * the ACPI table write functions. The first of ose would seem to be the right
* place, but other table write functions, e.g. the PIRQ table write function, are * place, but other table write functions, e.g. the PIRQ table write function, are
* called before the ACPI tables are written. This routine is called at the beginning * called before the ACPI tables are written. This routine is called at the beginning
* of each of the write functions called prior to the ACPI write functions, so this * of each of the write functions called prior to the ACPI write functions, so this
* becomes the best place for this call. * becomes the best place for this call.
*/ */
status = agesawrapper_amdinitlate(); status = agesawrapper_amdinitlate();
if(status) { if(status) {
printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
} }
sbdn_sb800 = 0; sbdn_sb800 = 0;
for (i = 0; i < 3; i++) { for (i = 0; i < 3; i++) {
bus_sb800[i] = 0; bus_sb800[i] = 0;
} }
for (i = 0; i < 256; i++) { for (i = 0; i < 256; i++) {
bus_type[i] = 0; /* default ISA bus. */ bus_type[i] = 0; /* default ISA bus. */
} }
bus_type[0] = 1; /* pci */ bus_type[0] = 1; /* pci */
// bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff; // bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff;
bus_sb800[0] = (pci1234x[0] >> 16) & 0xff; bus_sb800[0] = (pci1234x[0] >> 16) & 0xff;
/* sb800 */ /* sb800 */
dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4)); dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4));
if (dev) { if (dev) {
bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++; bus_isa++;
for (j = bus_sb800[1]; j < bus_isa; j++) for (j = bus_sb800[1]; j < bus_isa; j++)
bus_type[j] = 1; bus_type[j] = 1;
} }
for (i = 0; i < 4; i++) { for (i = 0; i < 4; i++) {
dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i)); dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i));
if (dev) { if (dev) {
bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++; bus_isa++;
} }
} }
for (j = bus_sb800[2]; j < bus_isa; j++) for (j = bus_sb800[2]; j < bus_isa; j++)
bus_type[j] = 1; bus_type[j] = 1;
/* I/O APICs: APIC ID Version State Address */ /* I/O APICs: APIC ID Version State Address */
bus_isa = 10; bus_isa = 10;
apicid_base = CONFIG_MAX_CPUS; apicid_base = CONFIG_MAX_CPUS;
apicid_sb800 = apicid_base; apicid_sb800 = apicid_base;
#if CONFIG_AMD_SB_CIMX #if CONFIG_AMD_SB_CIMX
sb_Late_Post(); sb_Late_Post();
#endif #endif
} }

6
src/mainboard/amd/inagua/irq_tables.c
View File

@ -27,9 +27,9 @@
static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
u8 slot, u8 rfu) u8 slot, u8 rfu)
{ {
pirq_info->bus = bus; pirq_info->bus = bus;
pirq_info->devfn = devfn; pirq_info->devfn = devfn;

30
src/mainboard/amd/inagua/mainboard.c
View File

@ -74,8 +74,8 @@ void set_pcie_dereset(void)
uint64_t uma_memory_base, uma_memory_size; uint64_t uma_memory_base, uma_memory_size;
/************************************************* /*************************************************
* enable the dedicated function in INAGUA board. * enable the dedicated function in INAGUA board.
*************************************************/ *************************************************/
static void inagua_enable(device_t dev) static void inagua_enable(device_t dev)
{ {
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
@ -87,14 +87,14 @@ static void inagua_enable(device_t dev)
/* TOP_MEM: the top of DRAM below 4G */ /* TOP_MEM: the top of DRAM below 4G */
msr = rdmsr(TOP_MEM); msr = rdmsr(TOP_MEM);
printk printk
(BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
__func__, msr.lo, msr.hi); __func__, msr.lo, msr.hi);
/* TOP_MEM2: the top of DRAM above 4G */ /* TOP_MEM2: the top of DRAM above 4G */
msr2 = rdmsr(TOP_MEM2); msr2 = rdmsr(TOP_MEM2);
printk printk
(BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
__func__, msr2.lo, msr2.hi); __func__, msr2.lo, msr2.hi);
/* refer to UMA Size Consideration in Family14h BKDG. */ /* refer to UMA Size Consideration in Family14h BKDG. */
sys_mem = msr.lo + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size, refer MemNGetUmaSizeON() sys_mem = msr.lo + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size, refer MemNGetUmaSizeON()
@ -102,16 +102,16 @@ static void inagua_enable(device_t dev)
uma_memory_size = 0x18000000; /* >= 2G memory, 384M recommended UMA */ uma_memory_size = 0x18000000; /* >= 2G memory, 384M recommended UMA */
} }
else { else {
if (sys_mem >= 0x40000000) { if (sys_mem >= 0x40000000) {
uma_memory_size = 0x10000000; /* >= 1G memory, 256M recommended UMA */ uma_memory_size = 0x10000000; /* >= 1G memory, 256M recommended UMA */
} else { } else {
uma_memory_size = 0x4000000; /* <1G memory, 64M recommended UMA */ uma_memory_size = 0x4000000; /* <1G memory, 64M recommended UMA */
} }
} }
uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */
printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
__func__, uma_memory_size, uma_memory_base); __func__, uma_memory_size, uma_memory_base);
/* TODO: TOP_MEM2 */ /* TODO: TOP_MEM2 */
#else #else
@ -127,16 +127,16 @@ int add_mainboard_resources(struct lb_memory *mem)
{ {
/* UMA is removed from system memory in the northbridge code, but /* UMA is removed from system memory in the northbridge code, but
* in some circumstances we want the memory mentioned as reserved. * in some circumstances we want the memory mentioned as reserved.
*/ */
#if (CONFIG_GFXUMA == 1) #if (CONFIG_GFXUMA == 1)
printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n", printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
uma_memory_base, uma_memory_size); uma_memory_base, uma_memory_size);
lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
uma_memory_size); uma_memory_size);
#endif #endif
return 0; return 0;
} }
struct chip_operations mainboard_ops = { struct chip_operations mainboard_ops = {
CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard") CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard")
.enable_dev = inagua_enable, .enable_dev = inagua_enable,
}; };

128
src/mainboard/amd/inagua/mptable.c
View File

@ -50,115 +50,115 @@ u8 intr_data[] = {
static void *smp_write_config_table(void *v) static void *smp_write_config_table(void *v)
{ {
struct mp_config_table *mc; struct mp_config_table *mc;
int bus_isa; int bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LAPIC_ADDR); mptable_init(mc, LAPIC_ADDR);
memcpy(mc->mpc_oem, "AMD ", 8); memcpy(mc->mpc_oem, "AMD ", 8);
smp_write_processors(mc); smp_write_processors(mc);
get_bus_conf(); get_bus_conf();
mptable_write_buses(mc, NULL, &bus_isa); mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */ /* I/O APICs: APIC ID Version State Address */
u32 dword; u32 dword;
u8 byte; u8 byte;
ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword); ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
dword &= 0xFFFFFFF0; dword &= 0xFFFFFFF0;
smp_write_ioapic(mc, apicid_sb800, 0x21, dword); smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
for (byte = 0x0; byte < sizeof(intr_data); byte ++) { for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00); outb(byte | 0x80, 0xC00);
outb(intr_data[byte], 0xC01); outb(intr_data[byte], 0xC01);
} }
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \ #define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0); mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
/* PCI interrupts are level triggered, and are /* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple. * associated with a specific bus/device/function tuple.
*/ */
#if CONFIG_GENERATE_ACPI_TABLES == 0 #if CONFIG_GENERATE_ACPI_TABLES == 0
#define PCI_INT(bus, dev, fn, pin) \ #define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
#else #else
#define PCI_INT(bus, dev, fn, pin) #define PCI_INT(bus, dev, fn, pin)
#endif #endif
/* APU Internal Graphic Device*/ /* APU Internal Graphic Device*/
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
PCI_INT(0x0, 0x14, 0x0, 0x10); PCI_INT(0x0, 0x14, 0x0, 0x10);
/* Southbridge HD Audio: */ /* Southbridge HD Audio: */
PCI_INT(0x0, 0x14, 0x2, 0x12); PCI_INT(0x0, 0x14, 0x2, 0x12);
PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */ PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
/* sata */ /* sata */
PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
/* on board NIC & Slot PCIE. */ /* on board NIC & Slot PCIE. */
/* PCI slots */ /* PCI slots */
/* PCI_SLOT 0. */ /* PCI_SLOT 0. */
PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14); PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15); PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16); PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17); PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */ /* PCI_SLOT 1. */
PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15); PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16); PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17); PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14); PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */ /* PCI_SLOT 2. */
PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16); PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17); PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14); PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15); PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12); PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12);
PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13); PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13);
PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14); PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14);
/* PCIe PortA */ /* PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, 0x10); PCI_INT(0x0, 0x15, 0x0, 0x10);
/* PCIe PortB */ /* PCIe PortB */
PCI_INT(0x0, 0x15, 0x1, 0x11); PCI_INT(0x0, 0x15, 0x1, 0x11);
/* PCIe PortC */ /* PCIe PortC */
PCI_INT(0x0, 0x15, 0x2, 0x12); PCI_INT(0x0, 0x15, 0x2, 0x12);
/* PCIe PortD */ /* PCIe PortD */
PCI_INT(0x0, 0x15, 0x3, 0x13); PCI_INT(0x0, 0x15, 0x3, 0x13);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */ /* There is no extension information... */
/* Compute the checksums */ /* Compute the checksums */
return mptable_finalize(mc); return mptable_finalize(mc);
} }
unsigned long write_smp_table(unsigned long addr) unsigned long write_smp_table(unsigned long addr)
{ {
void *v; void *v;
v = smp_write_floating_table(addr, 0); v = smp_write_floating_table(addr, 0);
return (unsigned long)smp_write_config_table(v); return (unsigned long)smp_write_config_table(v);
} }

8
src/mainboard/amd/inagua/platform_cfg.h
View File

@ -38,13 +38,13 @@
*/ */
#ifndef BIOS_SIZE #ifndef BIOS_SIZE
#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1 #if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
#define BIOS_SIZE BIOS_SIZE_1M #define BIOS_SIZE BIOS_SIZE_1M
#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1 #elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
#define BIOS_SIZE BIOS_SIZE_2M #define BIOS_SIZE BIOS_SIZE_2M
#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1 #elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1
#define BIOS_SIZE BIOS_SIZE_4M #define BIOS_SIZE BIOS_SIZE_4M
#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1 #elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1
#define BIOS_SIZE BIOS_SIZE_8M #define BIOS_SIZE BIOS_SIZE_8M
#endif #endif
#endif #endif