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src/mainboard/glkrvp: Fix ec_in_rw and wp 

Change-Id: I513b26d39973d9714b531d1ab0755c66d19eb332
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/22195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Shaunak Saha 2017-10-26 16:58:05 -07:00 committed by Martin Roth
parent 96939ae694
commit f08ed7d790
3 changed files with 4 additions and 10 deletions
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6
src/mainboard/intel/glkrvp/chromeos.c
View File

@ -30,8 +30,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
{-1, ACTIVE_HIGH, 0, "power"},
{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
{GPIO_EC_IN_RW, ACTIVE_HIGH,
gpio_get(GPIO_EC_IN_RW), "EC in RW"},
{-1, ACTIVE_HIGH, 0, "EC in RW"},
};
lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
}
@ -71,8 +70,7 @@ int clear_recovery_mode_switch(void)
int get_write_protect_state(void)
{
/* Read PCH_WP GPIO. */
return gpio_get(GPIO_PCH_WP);
return 0;
}
void mainboard_chromeos_acpi_generate(void)

4
src/mainboard/intel/glkrvp/variants/baseboard/gpio.c
View File

@ -284,8 +284,8 @@ variant_sleep_gpio_table(size_t *num)
static const struct cros_gpio cros_gpios[] = {
#if 0
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_COMM_NW_NAME),
CROS_GPIO_WP_AH(PAD_NW(GPIO_PCH_WP), GPIO_COMM_NW_NAME),
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
CROS_GPIO_WP_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
#endif
};

4
src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h
View File

@ -29,10 +29,6 @@
#define GPE_EC_WAKE GPE0_DW1_06
/* Write Protect and indication if EC is in RW code. */
#define GPIO_PCH_WP GPIO_75
#define GPIO_EC_IN_RW GPIO_41
/* Memory SKU GPIOs. */
#define MEM_CONFIG3 GPIO_45
#define MEM_CONFIG2 GPIO_38