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soc/intel/alderlake: Add GPIO Controller device ID for ADL-N 

Add PCH ACPI Device ID for Alder Lake N SOC GPIO Controller.
Document: Alder Lake N Platform EDS Volume 1 (Doc# 645548)

Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I6eb15751dd303b4b445cb64f25a040302e50c09d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
This commit is contained in:
Usha P 2022-01-18 13:37:15 +05:30 committed by Felix Held
parent 707aa2ae77
commit f1b11e7fcc
1 changed files with 5 additions and 0 deletions
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5
src/soc/intel/alderlake/include/soc/gpio.h
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@ -6,8 +6,13 @@
#include <soc/gpio_defs.h>
#include <intelblocks/gpio.h>
#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
#define CROS_GPIO_NAME "INTC1057"
#define CROS_GPIO_DEVICE_NAME "INTC1057:00"
#else
#define CROS_GPIO_NAME "INTC1055"
#define CROS_GPIO_DEVICE_NAME "INTC1055:00"
#endif
/* Enable GPIO community power management configuration */
#define MISCCFG_GPIO_PM_CONFIG_BITS (MISCCFG_GPVNNREQEN | \