soc/stoneyridge: Remove _PRW ASL
Remove _PRW GPE settings from GPP and USB ASL. The mainboard sets the GPEs. In addition, Stoney Ridge GPPs don't generate a GPE/SCIs. Change-Id: Ib6a07a997bc3508109a67867014210091efc0c99 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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@ -49,7 +49,6 @@ Device(AMRT) {
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/* Gpp 0 */
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Device(PBR4) {
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Name(_ADR, 0x00020001)
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Name(_PRW, Package() {0x18, 4})
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Method(_PRT,0) {
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If(PMOD){ Return(APS4) } /* APIC mode */
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Return (PS4) /* PIC Mode */
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@ -59,7 +58,6 @@ Device(PBR4) {
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/* Gpp 1 */
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Device(PBR5) {
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Name(_ADR, 0x00020002)
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Name(_PRW, Package() {0x18, 4})
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Method(_PRT,0) {
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If(PMOD){ Return(APS5) } /* APIC mode */
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Return (PS5) /* PIC Mode */
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@ -69,7 +67,6 @@ Device(PBR5) {
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/* Gpp 2 */
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Device(PBR6) {
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Name(_ADR, 0x00020003)
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Name(_PRW, Package() {0x18, 4})
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Method(_PRT,0) {
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If(PMOD){ Return(APS6) } /* APIC mode */
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Return (PS6) /* PIC Mode */
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@ -79,7 +76,6 @@ Device(PBR6) {
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/* Gpp 3 */
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Device(PBR7) {
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Name(_ADR, 0x00020004)
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Name(_PRW, Package() {0x18, 4})
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Method(_PRT,0) {
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If(PMOD){ Return(APS7) } /* APIC mode */
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Return (PS7) /* PIC Mode */
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@ -89,7 +85,6 @@ Device(PBR7) {
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/* Gpp 4 */
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Device(PBR8) {
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Name(_ADR, 0x00020005)
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Name(_PRW, Package() {0x18, 4})
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Method(_PRT,0) {
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If(PMOD){ Return(APS8) } /* APIC mode */
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Return (PS8) /* PIC Mode */
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@ -17,12 +17,10 @@
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/* 0:12.0 - EHCI */
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Device(EHC0) {
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Name(_ADR, 0x00120000)
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Name(_PRW, Package() {0x0b, 3})
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} /* end EHC0 */
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/* 0:10.0 - XHCI 0*/
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Device(XHC0) {
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Name(_ADR, 0x00100000)
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Name(_PRW, Package() {0x0b, 4})
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} /* end XHC0 */
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