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soc/amd/common/blk/pcie: Program LTR max latencies 

PCIe bridges need to provide the LTR (latency tolerance reporting)
maximum snoop/non-snoop values so that they are inherited by downstream
PCIe devices which support and enable LTR. Without this, downstream
devices cannot have LTR enabled, which is a requirement for supporting
PCIe L1 substates. Enabling L1ss without LTR has unpredictable behavior,
including some devices refusing to enter L1 low power modes at all.

Program the max snoop/non-snoop latency values for all PCIe bridges
using the same value used by AGESA/FSP, 1.049ms.

BUG=b:265890321
TEST=build/boot google/skyrim (multiple variants, NVMe drives), ensure
LTR is enabled, latency values are correctly set, and that device
power draw at idle is in the expected range (<25 mW).

Change-Id: Icf188e69cf5676be870873c56d175423d16704b4
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74288
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
This commit is contained in:
Matt DeVillier 2023-04-07 20:10:05 -05:00 committed by Martin Roth
parent 0d5b0248eb
commit f2e8865d76
1 changed files with 15 additions and 0 deletions
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15
src/soc/amd/common/block/pci/pcie_gpp.c
View File

@ -47,6 +47,20 @@ static void acpi_device_write_gpp_pci_dev(const struct device *dev)
acpigen_pop_len(); /* Scope */
}
/* Latency tolerance reporting, max snoop/non-snoop latency value 1.049ms */
#define PCIE_LTR_MAX_LATENCY_1049US 0x1001
static void pcie_get_ltr_max_latencies(u16 *max_snoop, u16 *max_nosnoop)
{
*max_snoop = PCIE_LTR_MAX_LATENCY_1049US;
*max_nosnoop = PCIE_LTR_MAX_LATENCY_1049US;
}
static struct pci_operations pcie_ops = {
.get_ltr_max_latencies = pcie_get_ltr_max_latencies,
.set_subsystem = pci_dev_set_subsystem,
};
struct device_operations amd_internal_pcie_gpp_ops = {
.read_resources = pci_bus_read_resources,
.set_resources = pci_dev_set_resources,
@ -65,4 +79,5 @@ struct device_operations amd_external_pcie_gpp_ops = {
.reset_bus = pci_bus_reset,
.acpi_name = pcie_gpp_acpi_name,
.acpi_fill_ssdt = acpi_device_write_gpp_pci_dev,
.ops_pci = &pcie_ops,
};