sb/intel/lynxpoint: Automatically generate the ACPI PCI routing table
This patch is based on a8a9f34e9b ("sb/intel/i82801{g,j}x:
Automatically generate ACPI PIRQ tables")
Tested on an ASRock H81M-HDS. The generated _PRT object looks correct,
and the system doesn't show any issue when running. The following
assignments occur:
ACPI_PIRQ_GEN: PCI: 00:02.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:03.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:14.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:16.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:1a.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:1b.0: pin=0 pirq=6
ACPI_PIRQ_GEN: PCI: 00:1c.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:1c.1: pin=1 pirq=1
ACPI_PIRQ_GEN: PCI: 00:1c.2: pin=2 pirq=2
ACPI_PIRQ_GEN: PCI: 00:1c.3: pin=3 pirq=3
ACPI_PIRQ_GEN: PCI: 00:1d.0: pin=0 pirq=7
ACPI_PIRQ_GEN: PCI: 00:1f.2: pin=1 pirq=3
ACPI_PIRQ_GEN: PCI: 00:1f.3: pin=2 pirq=2
Also tested on a Google Peppy board. The following assignments occur:
ACPI_PIRQ_GEN: PCI: 00:02.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:03.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:14.0: pin=0 pirq=2
ACPI_PIRQ_GEN: PCI: 00:1b.0: pin=0 pirq=6
ACPI_PIRQ_GEN: PCI: 00:1c.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:1d.0: pin=0 pirq=3
ACPI_PIRQ_GEN: PCI: 00:1f.2: pin=0 pirq=6
ACPI_PIRQ_GEN: PCI: 00:1f.3: pin=1 pirq=2
ACPI_PIRQ_GEN: PCI: 00:1f.6: pin=2 pirq=1
A diff of the _PRT object for the Google Peppy board is below. The code
used in the diff has been modified for clarity, but the semantics remain
the same. To summarise the diff:
* The disabled PCIe root ports are no longer included.
* The LPC controller is no longer included, as it has no interrupt pin.
The pins for the remaining LPC devices are each one less. Perhaps the
original _PRT object was incorrect?
* The SDIO device is no longer included, as it is disabled.
* The Serial IO devices are no longer included, but that is due to a
separate issue I am having with this system (the devices don't show up
under Linux regardless of this patch). In short: their omission is not
a fault of this patch.
--- pre/_PRT
+++ post/_PRT
@@ -1,301 +1,157 @@
Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
{
If (PICM)
{
- Return (Package (0x12)
+ Return (Package (0x09)
{
Package (0x04)
{
0x0002FFFF,
Zero,
Zero,
0x10
},
Package (0x04)
{
0x0003FFFF,
Zero,
Zero,
0x10
},
Package (0x04)
{
0x0014FFFF,
Zero,
Zero,
0x12
},
Package (0x04)
{
0x001BFFFF,
Zero,
Zero,
0x16
},
Package (0x04)
{
0x001CFFFF,
Zero,
Zero,
0x10
},
- Package (0x04)
- {
- 0x001CFFFF,
- One,
- Zero,
- 0x11
- },
-
- Package (0x04)
- {
- 0x001CFFFF,
- 0x02,
- Zero,
- 0x12
- },
-
- Package (0x04)
- {
- 0x001CFFFF,
- 0x03,
- Zero,
- 0x13
- },
-
Package (0x04)
{
0x001DFFFF,
Zero,
Zero,
0x13
},
Package (0x04)
{
0x001FFFFF,
Zero,
Zero,
0x16
},
Package (0x04)
{
0x001FFFFF,
One,
Zero,
0x12
},
Package (0x04)
{
0x001FFFFF,
0x02,
Zero,
0x11
- },
-
- Package (0x04)
- {
- 0x001FFFFF,
- 0x03,
- Zero,
- 0x10
- },
-
- Package (0x04)
- {
- 0x0015FFFF,
- Zero,
- Zero,
- 0x14
- },
-
- Package (0x04)
- {
- 0x0015FFFF,
- One,
- Zero,
- 0x15
- },
-
- Package (0x04)
- {
- 0x0015FFFF,
- 0x02,
- Zero,
- 0x15
- },
-
- Package (0x04)
- {
- 0x0015FFFF,
- 0x03,
- Zero,
- 0x15
- },
-
- Package (0x04)
- {
- 0x0017FFFF,
- Zero,
- Zero,
- 0x17
}
})
}
Else
{
- Return (Package (0x12)
+ Return (Package (0x09)
{
Package (0x04)
{
0x0002FFFF,
Zero,
^LPCB.LNKA,
Zero
},
Package (0x04)
{
0x0003FFFF,
Zero,
^LPCB.LNKA,
Zero
},
Package (0x04)
{
0x0014FFFF,
Zero,
^LPCB.LNKC,
Zero
},
Package (0x04)
{
0x001BFFFF,
Zero,
^LPCB.LNKG,
Zero
},
Package (0x04)
{
0x001CFFFF,
Zero,
^LPCB.LNKA,
Zero
},
- Package (0x04)
- {
- 0x001CFFFF,
- One,
- ^LPCB.LNKB,
- Zero
- },
-
- Package (0x04)
- {
- 0x001CFFFF,
- 0x02,
- ^LPCB.LNKC,
- Zero
- },
-
- Package (0x04)
- {
- 0x001CFFFF,
- 0x03,
- ^LPCB.LNKD,
- Zero
- },
-
Package (0x04)
{
0x001DFFFF,
Zero,
^LPCB.LNKD,
Zero
},
Package (0x04)
{
0x001FFFFF,
Zero,
^LPCB.LNKG,
Zero
},
Package (0x04)
{
0x001FFFFF,
One,
^LPCB.LNKC,
Zero
},
Package (0x04)
{
0x001FFFFF,
0x02,
^LPCB.LNKB,
Zero
- },
-
- Package (0x04)
- {
- 0x001FFFFF,
- 0x03,
- ^LPCB.LNKA,
- Zero
- },
-
- Package (0x04)
- {
- 0x0015FFFF,
- Zero,
- ^LPCB.LNKE,
- Zero
- },
-
- Package (0x04)
- {
- 0x0015FFFF,
- One,
- ^LPCB.LNKF,
- Zero
- },
-
- Package (0x04)
- {
- 0x0015FFFF,
- 0x02,
- ^LPCB.LNKF,
- Zero
- },
-
- Package (0x04)
- {
- 0x0015FFFF,
- 0x03,
- ^LPCB.LNKF,
- Zero
- },
-
- Package (0x04)
- {
- 0x0017FFFF,
- Zero,
- ^LPCB.LNKH,
- Zero
}
})
}
}
Change-Id: Id3f067cbf7c7d649fbbf774648d8ff928cb752a4
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Tristan Corrick
Nico Huber
parent
22f97009ad
commit
f3127d4af7
|
|
@ -1,82 +0,0 @@
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|||
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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||||
* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* This is board specific information: IRQ routing for Haswell */
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// PCI Interrupt Routing
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Method(_PRT)
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{
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If (PICM) {
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Return (Package() {
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// Onboard graphics (IGD) 0:2.0
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Package() { 0x0002ffff, 0, 0, 16 },
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// Mini-HD Audio 0:3.0
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Package() { 0x0003ffff, 0, 0, 16 },
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// High Definition Audio 0:1b.0
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Package() { 0x001bffff, 0, 0, 22 },
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// PCIe Root Ports 0:1c.x
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Package() { 0x001cffff, 0, 0, 16 },
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Package() { 0x001cffff, 1, 0, 17 },
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Package() { 0x001cffff, 2, 0, 18 },
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Package() { 0x001cffff, 3, 0, 19 },
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// EHCI 0:1d.0
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Package() { 0x001dffff, 0, 0, 19 },
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// XHCI 0:14.0
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Package() { 0x0014ffff, 0, 0, 18 },
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// LPC devices 0:1f.0
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Package() { 0x001fffff, 0, 0, 22 },
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Package() { 0x001fffff, 1, 0, 18 },
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Package() { 0x001fffff, 2, 0, 17 },
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Package() { 0x001fffff, 3, 0, 16 },
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// Serial IO 0:15.0
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Package() { 0x0015ffff, 0, 0, 20 },
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Package() { 0x0015ffff, 1, 0, 21 },
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Package() { 0x0015ffff, 2, 0, 21 },
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Package() { 0x0015ffff, 3, 0, 21 },
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// SDIO 0:17.0
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Package() { 0x0017ffff, 0, 0, 23 },
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})
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} Else {
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Return (Package() {
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// Onboard graphics (IGD) 0:2.0
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Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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// Mini-HD Audio 0:3.0
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Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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// High Definition Audio 0:1b.0
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Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
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// PCIe Root Ports 0:1c.x
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Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
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Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
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Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
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// EHCI 0:1d.0
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Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
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// XHCI 0:14.0
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Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
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// LPC device 0:1f.0
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Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
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Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
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Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
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Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
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// Serial IO 0:15.0
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Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
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Package() { 0x0015ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
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Package() { 0x0015ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 },
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Package() { 0x0015ffff, 3, \_SB.PCI0.LPCB.LNKF, 0 },
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// SDIO 0:17.0
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Package() { 0x0017ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
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})
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}
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}
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@ -1,82 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* This is board specific information: IRQ routing for Haswell */
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// PCI Interrupt Routing
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Method(_PRT)
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{
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If (PICM) {
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Return (Package() {
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// Onboard graphics (IGD) 0:2.0
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Package() { 0x0002ffff, 0, 0, 16 },
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// Mini-HD Audio 0:3.0
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Package() { 0x0003ffff, 0, 0, 16 },
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// High Definition Audio 0:1b.0
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Package() { 0x001bffff, 0, 0, 22 },
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// PCIe Root Ports 0:1c.x
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Package() { 0x001cffff, 0, 0, 16 },
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Package() { 0x001cffff, 1, 0, 17 },
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Package() { 0x001cffff, 2, 0, 18 },
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Package() { 0x001cffff, 3, 0, 19 },
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// EHCI 0:1d.0
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Package() { 0x001dffff, 0, 0, 19 },
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// XHCI 0:14.0
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Package() { 0x0014ffff, 0, 0, 18 },
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// LPC devices 0:1f.0
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Package() { 0x001fffff, 0, 0, 22 },
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Package() { 0x001fffff, 1, 0, 18 },
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Package() { 0x001fffff, 2, 0, 17 },
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Package() { 0x001fffff, 3, 0, 16 },
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// Serial IO 0:15.0
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Package() { 0x0015ffff, 0, 0, 20 },
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Package() { 0x0015ffff, 1, 0, 21 },
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Package() { 0x0015ffff, 2, 0, 21 },
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Package() { 0x0015ffff, 3, 0, 21 },
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// SDIO 0:17.0
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Package() { 0x0017ffff, 0, 0, 23 },
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})
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} Else {
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Return (Package() {
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// Onboard graphics (IGD) 0:2.0
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Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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// Mini-HD Audio 0:3.0
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Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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// High Definition Audio 0:1b.0
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Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
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// PCIe Root Ports 0:1c.x
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Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
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Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
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Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
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// EHCI 0:1d.0
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Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
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// XHCI 0:14.0
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Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
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// LPC device 0:1f.0
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Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
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Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
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Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
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Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
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// Serial IO 0:15.0
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Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
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Package() { 0x0015ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
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Package() { 0x0015ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 },
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Package() { 0x0015ffff, 3, \_SB.PCI0.LPCB.LNKF, 0 },
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// SDIO 0:17.0
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Package() { 0x0017ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
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})
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}
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}
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@ -1,64 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* This is board specific information: IRQ routing for IvyBridge */
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// PCI Interrupt Routing
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Method(_PRT)
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{
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If (PICM) {
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Return (Package() {
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// Onboard graphics (IGD) 0:2.0
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Package() { 0x0002ffff, 0, 0, 16 },
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// High Definition Audio 0:1b.0
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Package() { 0x001bffff, 0, 0, 22 },
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// PCIe Root Ports 0:1c.x
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Package() { 0x001cffff, 0, 0, 17 },
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Package() { 0x001cffff, 1, 0, 18 },
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Package() { 0x001cffff, 2, 0, 19 },
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Package() { 0x001cffff, 3, 0, 20 },
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// EHCI #1 0:1d.0
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Package() { 0x001dffff, 0, 0, 19 },
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// EHCI #2 0:1a.0
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Package() { 0x001affff, 0, 0, 20 },
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// LPC devices 0:1f.0
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Package() { 0x001fffff, 0, 0, 21 },
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Package() { 0x001fffff, 1, 0, 22 },
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Package() { 0x001fffff, 2, 0, 23 },
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Package() { 0x001fffff, 3, 0, 16 },
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})
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} Else {
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Return (Package() {
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// Onboard graphics (IGD) 0:2.0
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Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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// High Definition Audio 0:1b.0
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Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
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// PCIe Root Ports 0:1c.x
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Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
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Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
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Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
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Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 },
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// EHCI #1 0:1d.0
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Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
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// EHCI #2 0:1a.0
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Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
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// LPC device 0:1f.0
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Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
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Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 },
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Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 },
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Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
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})
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}
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}
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@ -455,6 +455,3 @@ Method (_CRS, 0, Serialized)
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Return (MCRS)
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}
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/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */
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#include "acpi/haswell_pci_irqs.asl"
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|
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@ -74,6 +74,22 @@ static void pci_domain_set_resources(struct device *dev)
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assign_resources(dev->link_list);
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}
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static const char *northbridge_acpi_name(const struct device *dev)
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{
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if (dev->path.type == DEVICE_PATH_DOMAIN)
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return "PCI0";
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if (dev->path.type != DEVICE_PATH_PCI || dev->bus->secondary != 0)
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return NULL;
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switch (dev->path.pci.devfn) {
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case PCI_DEVFN(0, 0):
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return "MCHC";
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||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* TODO We could determine how many PCIe busses we need in
|
||||
* the bar. For now that number is hardcoded to a max of 64.
|
||||
* See e7525/northbridge.c for an example.
|
||||
|
|
@ -84,6 +100,7 @@ static struct device_operations pci_domain_ops = {
|
|||
.enable_resources = NULL,
|
||||
.init = NULL,
|
||||
.scan_bus = pci_domain_scan_bus,
|
||||
.acpi_name = northbridge_acpi_name,
|
||||
.write_acpi_tables = northbridge_write_acpi_tables,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -33,6 +33,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
|
|||
select HAVE_SPI_CONSOLE_SUPPORT
|
||||
select RTC
|
||||
select SOUTHBRIDGE_INTEL_COMMON_GPIO if !INTEL_LYNXPOINT_LP
|
||||
select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
|
||||
select HAVE_INTEL_CHIPSET_LOCKDOWN
|
||||
|
||||
config INTEL_LYNXPOINT_LP
|
||||
|
|
|
|||
|
|
@ -36,6 +36,7 @@
|
|||
#include <arch/acpigen.h>
|
||||
#include <cbmem.h>
|
||||
#include <drivers/intel/gma/i915.h>
|
||||
#include <southbridge/intel/common/acpi_pirq_gen.h>
|
||||
|
||||
#define NMI_OFF 0
|
||||
|
||||
|
|
@ -789,6 +790,16 @@ static void southbridge_inject_dsdt(struct device *dev)
|
|||
}
|
||||
}
|
||||
|
||||
static const char *lpc_acpi_name(const struct device *dev)
|
||||
{
|
||||
return "LPCB";
|
||||
}
|
||||
|
||||
static void southbridge_fill_ssdt(struct device *dev)
|
||||
{
|
||||
intel_acpi_gen_def_acpi_pirq(dev);
|
||||
}
|
||||
|
||||
static unsigned long southbridge_write_acpi_tables(struct device *device,
|
||||
unsigned long start,
|
||||
struct acpi_rsdp *rsdp)
|
||||
|
|
@ -835,7 +846,9 @@ static struct device_operations device_ops = {
|
|||
.read_resources = pch_lpc_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.acpi_fill_ssdt_generator = southbridge_fill_ssdt,
|
||||
.acpi_inject_dsdt_generator = southbridge_inject_dsdt,
|
||||
.acpi_name = lpc_acpi_name,
|
||||
.write_acpi_tables = southbridge_write_acpi_tables,
|
||||
.init = lpc_init,
|
||||
.enable = pch_lpc_enable,
|
||||
|
|
|
|||
Loading…
Reference in New Issue