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Tristan Corrick f3127d4af7 sb/intel/lynxpoint: Automatically generate the ACPI PCI routing table 
This patch is based on a8a9f34e9b ("sb/intel/i82801{g,j}x:
Automatically generate ACPI PIRQ tables")

Tested on an ASRock H81M-HDS. The generated _PRT object looks correct,
and the system doesn't show any issue when running. The following
assignments occur:

	ACPI_PIRQ_GEN: PCI: 00:02.0: pin=0 pirq=0
	ACPI_PIRQ_GEN: PCI: 00:03.0: pin=0 pirq=0
	ACPI_PIRQ_GEN: PCI: 00:14.0: pin=0 pirq=0
	ACPI_PIRQ_GEN: PCI: 00:16.0: pin=0 pirq=0
	ACPI_PIRQ_GEN: PCI: 00:1a.0: pin=0 pirq=0
	ACPI_PIRQ_GEN: PCI: 00:1b.0: pin=0 pirq=6
	ACPI_PIRQ_GEN: PCI: 00:1c.0: pin=0 pirq=0
	ACPI_PIRQ_GEN: PCI: 00:1c.1: pin=1 pirq=1
	ACPI_PIRQ_GEN: PCI: 00:1c.2: pin=2 pirq=2
	ACPI_PIRQ_GEN: PCI: 00:1c.3: pin=3 pirq=3
	ACPI_PIRQ_GEN: PCI: 00:1d.0: pin=0 pirq=7
	ACPI_PIRQ_GEN: PCI: 00:1f.2: pin=1 pirq=3
	ACPI_PIRQ_GEN: PCI: 00:1f.3: pin=2 pirq=2

Also tested on a Google Peppy board. The following assignments occur:

	ACPI_PIRQ_GEN: PCI: 00:02.0: pin=0 pirq=0
	ACPI_PIRQ_GEN: PCI: 00:03.0: pin=0 pirq=0
	ACPI_PIRQ_GEN: PCI: 00:14.0: pin=0 pirq=2
	ACPI_PIRQ_GEN: PCI: 00:1b.0: pin=0 pirq=6
	ACPI_PIRQ_GEN: PCI: 00:1c.0: pin=0 pirq=0
	ACPI_PIRQ_GEN: PCI: 00:1d.0: pin=0 pirq=3
	ACPI_PIRQ_GEN: PCI: 00:1f.2: pin=0 pirq=6
	ACPI_PIRQ_GEN: PCI: 00:1f.3: pin=1 pirq=2
	ACPI_PIRQ_GEN: PCI: 00:1f.6: pin=2 pirq=1

A diff of the _PRT object for the Google Peppy board is below. The code
used in the diff has been modified for clarity, but the semantics remain
the same. To summarise the diff:

* The disabled PCIe root ports are no longer included.

* The LPC controller is no longer included, as it has no interrupt pin.
  The pins for the remaining LPC devices are each one less. Perhaps the
  original _PRT object was incorrect?

* The SDIO device is no longer included, as it is disabled.

* The Serial IO devices are no longer included, but that is due to a
  separate issue I am having with this system (the devices don't show up
  under Linux regardless of this patch). In short: their omission is not
  a fault of this patch.

--- pre/_PRT
+++ post/_PRT
@@ -1,301 +1,157 @@
         Method (_PRT, 0, NotSerialized)  // _PRT: PCI Routing Table
         {
             If (PICM)
             {
-                Return (Package (0x12)
+                Return (Package (0x09)
                 {
                     Package (0x04)
                     {
                         0x0002FFFF,
                         Zero,
                         Zero,
                         0x10
                     },

                     Package (0x04)
                     {
                         0x0003FFFF,
                         Zero,
                         Zero,
                         0x10
                     },

                     Package (0x04)
                     {
                         0x0014FFFF,
                         Zero,
                         Zero,
                         0x12
                     },

                     Package (0x04)
                     {
                         0x001BFFFF,
                         Zero,
                         Zero,
                         0x16
                     },

                     Package (0x04)
                     {
                         0x001CFFFF,
                         Zero,
                         Zero,
                         0x10
                     },

-                    Package (0x04)
-                    {
-                        0x001CFFFF,
-                        One,
-                        Zero,
-                        0x11
-                    },
-
-                    Package (0x04)
-                    {
-                        0x001CFFFF,
-                        0x02,
-                        Zero,
-                        0x12
-                    },
-
-                    Package (0x04)
-                    {
-                        0x001CFFFF,
-                        0x03,
-                        Zero,
-                        0x13
-                    },
-
                     Package (0x04)
                     {
                         0x001DFFFF,
                         Zero,
                         Zero,
                         0x13
                     },

                     Package (0x04)
                     {
                         0x001FFFFF,
                         Zero,
                         Zero,
                         0x16
                     },

                     Package (0x04)
                     {
                         0x001FFFFF,
                         One,
                         Zero,
                         0x12
                     },

                     Package (0x04)
                     {
                         0x001FFFFF,
                         0x02,
                         Zero,
                         0x11
-                    },
-
-                    Package (0x04)
-                    {
-                        0x001FFFFF,
-                        0x03,
-                        Zero,
-                        0x10
-                    },
-
-                    Package (0x04)
-                    {
-                        0x0015FFFF,
-                        Zero,
-                        Zero,
-                        0x14
-                    },
-
-                    Package (0x04)
-                    {
-                        0x0015FFFF,
-                        One,
-                        Zero,
-                        0x15
-                    },
-
-                    Package (0x04)
-                    {
-                        0x0015FFFF,
-                        0x02,
-                        Zero,
-                        0x15
-                    },
-
-                    Package (0x04)
-                    {
-                        0x0015FFFF,
-                        0x03,
-                        Zero,
-                        0x15
-                    },
-
-                    Package (0x04)
-                    {
-                        0x0017FFFF,
-                        Zero,
-                        Zero,
-                        0x17
                     }
                 })
             }
             Else
             {
-                Return (Package (0x12)
+                Return (Package (0x09)
                 {
                     Package (0x04)
                     {
                         0x0002FFFF,
                         Zero,
                         ^LPCB.LNKA,
                         Zero
                     },

                     Package (0x04)
                     {
                         0x0003FFFF,
                         Zero,
                         ^LPCB.LNKA,
                         Zero
                     },

                     Package (0x04)
                     {
                         0x0014FFFF,
                         Zero,
                         ^LPCB.LNKC,
                         Zero
                     },

                     Package (0x04)
                     {
                         0x001BFFFF,
                         Zero,
                         ^LPCB.LNKG,
                         Zero
                     },

                     Package (0x04)
                     {
                         0x001CFFFF,
                         Zero,
                         ^LPCB.LNKA,
                         Zero
                     },

-                    Package (0x04)
-                    {
-                        0x001CFFFF,
-                        One,
-                        ^LPCB.LNKB,
-                        Zero
-                    },
-
-                    Package (0x04)
-                    {
-                        0x001CFFFF,
-                        0x02,
-                        ^LPCB.LNKC,
-                        Zero
-                    },
-
-                    Package (0x04)
-                    {
-                        0x001CFFFF,
-                        0x03,
-                        ^LPCB.LNKD,
-                        Zero
-                    },
-
                     Package (0x04)
                     {
                         0x001DFFFF,
                         Zero,
                         ^LPCB.LNKD,
                         Zero
                     },

                     Package (0x04)
                     {
                         0x001FFFFF,
                         Zero,
                         ^LPCB.LNKG,
                         Zero
                     },

                     Package (0x04)
                     {
                         0x001FFFFF,
                         One,
                         ^LPCB.LNKC,
                         Zero
                     },

                     Package (0x04)
                     {
                         0x001FFFFF,
                         0x02,
                         ^LPCB.LNKB,
                         Zero
-                    },
-
-                    Package (0x04)
-                    {
-                        0x001FFFFF,
-                        0x03,
-                        ^LPCB.LNKA,
-                        Zero
-                    },
-
-                    Package (0x04)
-                    {
-                        0x0015FFFF,
-                        Zero,
-                        ^LPCB.LNKE,
-                        Zero
-                    },
-
-                    Package (0x04)
-                    {
-                        0x0015FFFF,
-                        One,
-                        ^LPCB.LNKF,
-                        Zero
-                    },
-
-                    Package (0x04)
-                    {
-                        0x0015FFFF,
-                        0x02,
-                        ^LPCB.LNKF,
-                        Zero
-                    },
-
-                    Package (0x04)
-                    {
-                        0x0015FFFF,
-                        0x03,
-                        ^LPCB.LNKF,
-                        Zero
-                    },
-
-                    Package (0x04)
-                    {
-                        0x0017FFFF,
-                        Zero,
-                        ^LPCB.LNKH,
-                        Zero
                     }
                 })
             }
         }

Change-Id: Id3f067cbf7c7d649fbbf774648d8ff928cb752a4
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 		2018-11-01 22:22:12 +00:00
3rdparty 3rdparty/blobs: Update to include QuarkFsp 2018-10-12 23:21:35 +00:00
Documentation Documentation/riscv: Improve `index.md` 2018-10-30 02:10:44 +00:00
configs soc/intel/apollolake: Add reset code to postcar stage 2018-10-23 07:11:31 +00:00
payloads libpayload: Fill reg_base for debugging purposes 2018-10-23 06:24:47 +00:00
src sb/intel/lynxpoint: Automatically generate the ACPI PCI routing table 2018-11-01 22:22:12 +00:00
util util/bincfg: code cleanup: convert sym_table to a local variable 2018-10-24 10:02:06 +00:00
.checkpatch.conf .checkpatch.conf: Ignore a few more warnings 2018-08-13 12:23:24 +00:00
.clang-format clang-format: change it to better match our style 2018-07-31 23:25:29 +00:00
.gitignore .gitignore: Spell Documentation in uppercase 2018-10-10 12:16:13 +00:00
.gitmodules submodules: add FSP mirror as non-default submodule 2018-09-02 03:07:50 +00:00
.gitreview
…
COPYING
…
MAINTAINERS MAINTAINERS: Update RISC-V entry with SiFive and utils 2018-10-04 09:38:50 +00:00
Makefile Makefile: Enable DELETE_ON_ERROR for all targets 2018-08-08 21:57:07 +00:00
Makefile.inc build system: Fix FSP downloading 2018-10-27 11:12:09 +00:00
README.md README: Convert to Markdown 2018-09-16 13:01:58 +00:00
gnat.adc
…
toolchain.inc Introduce bootblock self-decompression 2018-05-22 02:44:14 +00:00

README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

Copyright and License

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.