sb/intel/lynxpoint: Automatically generate the ACPI PCI routing table
This patch is based on a8a9f34e9b ("sb/intel/i82801{g,j}x:
Automatically generate ACPI PIRQ tables")
Tested on an ASRock H81M-HDS. The generated _PRT object looks correct,
and the system doesn't show any issue when running. The following
assignments occur:
ACPI_PIRQ_GEN: PCI: 00:02.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:03.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:14.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:16.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:1a.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:1b.0: pin=0 pirq=6
ACPI_PIRQ_GEN: PCI: 00:1c.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:1c.1: pin=1 pirq=1
ACPI_PIRQ_GEN: PCI: 00:1c.2: pin=2 pirq=2
ACPI_PIRQ_GEN: PCI: 00:1c.3: pin=3 pirq=3
ACPI_PIRQ_GEN: PCI: 00:1d.0: pin=0 pirq=7
ACPI_PIRQ_GEN: PCI: 00:1f.2: pin=1 pirq=3
ACPI_PIRQ_GEN: PCI: 00:1f.3: pin=2 pirq=2
Also tested on a Google Peppy board. The following assignments occur:
ACPI_PIRQ_GEN: PCI: 00:02.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:03.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:14.0: pin=0 pirq=2
ACPI_PIRQ_GEN: PCI: 00:1b.0: pin=0 pirq=6
ACPI_PIRQ_GEN: PCI: 00:1c.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:1d.0: pin=0 pirq=3
ACPI_PIRQ_GEN: PCI: 00:1f.2: pin=0 pirq=6
ACPI_PIRQ_GEN: PCI: 00:1f.3: pin=1 pirq=2
ACPI_PIRQ_GEN: PCI: 00:1f.6: pin=2 pirq=1
A diff of the _PRT object for the Google Peppy board is below. The code
used in the diff has been modified for clarity, but the semantics remain
the same. To summarise the diff:
* The disabled PCIe root ports are no longer included.
* The LPC controller is no longer included, as it has no interrupt pin.
The pins for the remaining LPC devices are each one less. Perhaps the
original _PRT object was incorrect?
* The SDIO device is no longer included, as it is disabled.
* The Serial IO devices are no longer included, but that is due to a
separate issue I am having with this system (the devices don't show up
under Linux regardless of this patch). In short: their omission is not
a fault of this patch.
--- pre/_PRT
+++ post/_PRT
@@ -1,301 +1,157 @@
Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
{
If (PICM)
{
- Return (Package (0x12)
+ Return (Package (0x09)
{
Package (0x04)
{
0x0002FFFF,
Zero,
Zero,
0x10
},
Package (0x04)
{
0x0003FFFF,
Zero,
Zero,
0x10
},
Package (0x04)
{
0x0014FFFF,
Zero,
Zero,
0x12
},
Package (0x04)
{
0x001BFFFF,
Zero,
Zero,
0x16
},
Package (0x04)
{
0x001CFFFF,
Zero,
Zero,
0x10
},
- Package (0x04)
- {
- 0x001CFFFF,
- One,
- Zero,
- 0x11
- },
-
- Package (0x04)
- {
- 0x001CFFFF,
- 0x02,
- Zero,
- 0x12
- },
-
- Package (0x04)
- {
- 0x001CFFFF,
- 0x03,
- Zero,
- 0x13
- },
-
Package (0x04)
{
0x001DFFFF,
Zero,
Zero,
0x13
},
Package (0x04)
{
0x001FFFFF,
Zero,
Zero,
0x16
},
Package (0x04)
{
0x001FFFFF,
One,
Zero,
0x12
},
Package (0x04)
{
0x001FFFFF,
0x02,
Zero,
0x11
- },
-
- Package (0x04)
- {
- 0x001FFFFF,
- 0x03,
- Zero,
- 0x10
- },
-
- Package (0x04)
- {
- 0x0015FFFF,
- Zero,
- Zero,
- 0x14
- },
-
- Package (0x04)
- {
- 0x0015FFFF,
- One,
- Zero,
- 0x15
- },
-
- Package (0x04)
- {
- 0x0015FFFF,
- 0x02,
- Zero,
- 0x15
- },
-
- Package (0x04)
- {
- 0x0015FFFF,
- 0x03,
- Zero,
- 0x15
- },
-
- Package (0x04)
- {
- 0x0017FFFF,
- Zero,
- Zero,
- 0x17
}
})
}
Else
{
- Return (Package (0x12)
+ Return (Package (0x09)
{
Package (0x04)
{
0x0002FFFF,
Zero,
^LPCB.LNKA,
Zero
},
Package (0x04)
{
0x0003FFFF,
Zero,
^LPCB.LNKA,
Zero
},
Package (0x04)
{
0x0014FFFF,
Zero,
^LPCB.LNKC,
Zero
},
Package (0x04)
{
0x001BFFFF,
Zero,
^LPCB.LNKG,
Zero
},
Package (0x04)
{
0x001CFFFF,
Zero,
^LPCB.LNKA,
Zero
},
- Package (0x04)
- {
- 0x001CFFFF,
- One,
- ^LPCB.LNKB,
- Zero
- },
-
- Package (0x04)
- {
- 0x001CFFFF,
- 0x02,
- ^LPCB.LNKC,
- Zero
- },
-
- Package (0x04)
- {
- 0x001CFFFF,
- 0x03,
- ^LPCB.LNKD,
- Zero
- },
-
Package (0x04)
{
0x001DFFFF,
Zero,
^LPCB.LNKD,
Zero
},
Package (0x04)
{
0x001FFFFF,
Zero,
^LPCB.LNKG,
Zero
},
Package (0x04)
{
0x001FFFFF,
One,
^LPCB.LNKC,
Zero
},
Package (0x04)
{
0x001FFFFF,
0x02,
^LPCB.LNKB,
Zero
- },
-
- Package (0x04)
- {
- 0x001FFFFF,
- 0x03,
- ^LPCB.LNKA,
- Zero
- },
-
- Package (0x04)
- {
- 0x0015FFFF,
- Zero,
- ^LPCB.LNKE,
- Zero
- },
-
- Package (0x04)
- {
- 0x0015FFFF,
- One,
- ^LPCB.LNKF,
- Zero
- },
-
- Package (0x04)
- {
- 0x0015FFFF,
- 0x02,
- ^LPCB.LNKF,
- Zero
- },
-
- Package (0x04)
- {
- 0x0015FFFF,
- 0x03,
- ^LPCB.LNKF,
- Zero
- },
-
- Package (0x04)
- {
- 0x0017FFFF,
- Zero,
- ^LPCB.LNKH,
- Zero
}
})
}
}
Change-Id: Id3f067cbf7c7d649fbbf774648d8ff928cb752a4
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Tristan Corrick
Nico Huber
parent
22f97009ad
commit
f3127d4af7
|
|
@ -1,82 +0,0 @@
|
||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2007-2009 coresystems GmbH
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* This is board specific information: IRQ routing for Haswell */
|
|
||||||
|
|
||||||
// PCI Interrupt Routing
|
|
||||||
Method(_PRT)
|
|
||||||
{
|
|
||||||
If (PICM) {
|
|
||||||
Return (Package() {
|
|
||||||
// Onboard graphics (IGD) 0:2.0
|
|
||||||
Package() { 0x0002ffff, 0, 0, 16 },
|
|
||||||
// Mini-HD Audio 0:3.0
|
|
||||||
Package() { 0x0003ffff, 0, 0, 16 },
|
|
||||||
// High Definition Audio 0:1b.0
|
|
||||||
Package() { 0x001bffff, 0, 0, 22 },
|
|
||||||
// PCIe Root Ports 0:1c.x
|
|
||||||
Package() { 0x001cffff, 0, 0, 16 },
|
|
||||||
Package() { 0x001cffff, 1, 0, 17 },
|
|
||||||
Package() { 0x001cffff, 2, 0, 18 },
|
|
||||||
Package() { 0x001cffff, 3, 0, 19 },
|
|
||||||
// EHCI 0:1d.0
|
|
||||||
Package() { 0x001dffff, 0, 0, 19 },
|
|
||||||
// XHCI 0:14.0
|
|
||||||
Package() { 0x0014ffff, 0, 0, 18 },
|
|
||||||
// LPC devices 0:1f.0
|
|
||||||
Package() { 0x001fffff, 0, 0, 22 },
|
|
||||||
Package() { 0x001fffff, 1, 0, 18 },
|
|
||||||
Package() { 0x001fffff, 2, 0, 17 },
|
|
||||||
Package() { 0x001fffff, 3, 0, 16 },
|
|
||||||
// Serial IO 0:15.0
|
|
||||||
Package() { 0x0015ffff, 0, 0, 20 },
|
|
||||||
Package() { 0x0015ffff, 1, 0, 21 },
|
|
||||||
Package() { 0x0015ffff, 2, 0, 21 },
|
|
||||||
Package() { 0x0015ffff, 3, 0, 21 },
|
|
||||||
// SDIO 0:17.0
|
|
||||||
Package() { 0x0017ffff, 0, 0, 23 },
|
|
||||||
})
|
|
||||||
} Else {
|
|
||||||
Return (Package() {
|
|
||||||
// Onboard graphics (IGD) 0:2.0
|
|
||||||
Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
|
|
||||||
// Mini-HD Audio 0:3.0
|
|
||||||
Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
|
|
||||||
// High Definition Audio 0:1b.0
|
|
||||||
Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
|
|
||||||
// PCIe Root Ports 0:1c.x
|
|
||||||
Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
|
|
||||||
Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
|
|
||||||
Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
|
|
||||||
Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
|
|
||||||
// EHCI 0:1d.0
|
|
||||||
Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
|
|
||||||
// XHCI 0:14.0
|
|
||||||
Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
|
|
||||||
// LPC device 0:1f.0
|
|
||||||
Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
|
|
||||||
Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
|
|
||||||
Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
|
|
||||||
Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
|
|
||||||
// Serial IO 0:15.0
|
|
||||||
Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
|
|
||||||
Package() { 0x0015ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
|
|
||||||
Package() { 0x0015ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 },
|
|
||||||
Package() { 0x0015ffff, 3, \_SB.PCI0.LPCB.LNKF, 0 },
|
|
||||||
// SDIO 0:17.0
|
|
||||||
Package() { 0x0017ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
|
|
||||||
})
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
@ -1,82 +0,0 @@
|
||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2007-2009 coresystems GmbH
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* This is board specific information: IRQ routing for Haswell */
|
|
||||||
|
|
||||||
// PCI Interrupt Routing
|
|
||||||
Method(_PRT)
|
|
||||||
{
|
|
||||||
If (PICM) {
|
|
||||||
Return (Package() {
|
|
||||||
// Onboard graphics (IGD) 0:2.0
|
|
||||||
Package() { 0x0002ffff, 0, 0, 16 },
|
|
||||||
// Mini-HD Audio 0:3.0
|
|
||||||
Package() { 0x0003ffff, 0, 0, 16 },
|
|
||||||
// High Definition Audio 0:1b.0
|
|
||||||
Package() { 0x001bffff, 0, 0, 22 },
|
|
||||||
// PCIe Root Ports 0:1c.x
|
|
||||||
Package() { 0x001cffff, 0, 0, 16 },
|
|
||||||
Package() { 0x001cffff, 1, 0, 17 },
|
|
||||||
Package() { 0x001cffff, 2, 0, 18 },
|
|
||||||
Package() { 0x001cffff, 3, 0, 19 },
|
|
||||||
// EHCI 0:1d.0
|
|
||||||
Package() { 0x001dffff, 0, 0, 19 },
|
|
||||||
// XHCI 0:14.0
|
|
||||||
Package() { 0x0014ffff, 0, 0, 18 },
|
|
||||||
// LPC devices 0:1f.0
|
|
||||||
Package() { 0x001fffff, 0, 0, 22 },
|
|
||||||
Package() { 0x001fffff, 1, 0, 18 },
|
|
||||||
Package() { 0x001fffff, 2, 0, 17 },
|
|
||||||
Package() { 0x001fffff, 3, 0, 16 },
|
|
||||||
// Serial IO 0:15.0
|
|
||||||
Package() { 0x0015ffff, 0, 0, 20 },
|
|
||||||
Package() { 0x0015ffff, 1, 0, 21 },
|
|
||||||
Package() { 0x0015ffff, 2, 0, 21 },
|
|
||||||
Package() { 0x0015ffff, 3, 0, 21 },
|
|
||||||
// SDIO 0:17.0
|
|
||||||
Package() { 0x0017ffff, 0, 0, 23 },
|
|
||||||
})
|
|
||||||
} Else {
|
|
||||||
Return (Package() {
|
|
||||||
// Onboard graphics (IGD) 0:2.0
|
|
||||||
Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
|
|
||||||
// Mini-HD Audio 0:3.0
|
|
||||||
Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
|
|
||||||
// High Definition Audio 0:1b.0
|
|
||||||
Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
|
|
||||||
// PCIe Root Ports 0:1c.x
|
|
||||||
Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
|
|
||||||
Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
|
|
||||||
Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
|
|
||||||
Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
|
|
||||||
// EHCI 0:1d.0
|
|
||||||
Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
|
|
||||||
// XHCI 0:14.0
|
|
||||||
Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
|
|
||||||
// LPC device 0:1f.0
|
|
||||||
Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
|
|
||||||
Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
|
|
||||||
Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
|
|
||||||
Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
|
|
||||||
// Serial IO 0:15.0
|
|
||||||
Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
|
|
||||||
Package() { 0x0015ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
|
|
||||||
Package() { 0x0015ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 },
|
|
||||||
Package() { 0x0015ffff, 3, \_SB.PCI0.LPCB.LNKF, 0 },
|
|
||||||
// SDIO 0:17.0
|
|
||||||
Package() { 0x0017ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
|
|
||||||
})
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
@ -1,64 +0,0 @@
|
||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2007-2009 coresystems GmbH
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* This is board specific information: IRQ routing for IvyBridge */
|
|
||||||
|
|
||||||
// PCI Interrupt Routing
|
|
||||||
Method(_PRT)
|
|
||||||
{
|
|
||||||
If (PICM) {
|
|
||||||
Return (Package() {
|
|
||||||
// Onboard graphics (IGD) 0:2.0
|
|
||||||
Package() { 0x0002ffff, 0, 0, 16 },
|
|
||||||
// High Definition Audio 0:1b.0
|
|
||||||
Package() { 0x001bffff, 0, 0, 22 },
|
|
||||||
// PCIe Root Ports 0:1c.x
|
|
||||||
Package() { 0x001cffff, 0, 0, 17 },
|
|
||||||
Package() { 0x001cffff, 1, 0, 18 },
|
|
||||||
Package() { 0x001cffff, 2, 0, 19 },
|
|
||||||
Package() { 0x001cffff, 3, 0, 20 },
|
|
||||||
// EHCI #1 0:1d.0
|
|
||||||
Package() { 0x001dffff, 0, 0, 19 },
|
|
||||||
// EHCI #2 0:1a.0
|
|
||||||
Package() { 0x001affff, 0, 0, 20 },
|
|
||||||
// LPC devices 0:1f.0
|
|
||||||
Package() { 0x001fffff, 0, 0, 21 },
|
|
||||||
Package() { 0x001fffff, 1, 0, 22 },
|
|
||||||
Package() { 0x001fffff, 2, 0, 23 },
|
|
||||||
Package() { 0x001fffff, 3, 0, 16 },
|
|
||||||
})
|
|
||||||
} Else {
|
|
||||||
Return (Package() {
|
|
||||||
// Onboard graphics (IGD) 0:2.0
|
|
||||||
Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
|
|
||||||
// High Definition Audio 0:1b.0
|
|
||||||
Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
|
|
||||||
// PCIe Root Ports 0:1c.x
|
|
||||||
Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
|
|
||||||
Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
|
|
||||||
Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
|
|
||||||
Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 },
|
|
||||||
// EHCI #1 0:1d.0
|
|
||||||
Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
|
|
||||||
// EHCI #2 0:1a.0
|
|
||||||
Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
|
|
||||||
// LPC device 0:1f.0
|
|
||||||
Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
|
|
||||||
Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 },
|
|
||||||
Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 },
|
|
||||||
Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
|
|
||||||
})
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
@ -455,6 +455,3 @@ Method (_CRS, 0, Serialized)
|
||||||
|
|
||||||
Return (MCRS)
|
Return (MCRS)
|
||||||
}
|
}
|
||||||
|
|
||||||
/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */
|
|
||||||
#include "acpi/haswell_pci_irqs.asl"
|
|
||||||
|
|
|
||||||
|
|
@ -74,6 +74,22 @@ static void pci_domain_set_resources(struct device *dev)
|
||||||
assign_resources(dev->link_list);
|
assign_resources(dev->link_list);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static const char *northbridge_acpi_name(const struct device *dev)
|
||||||
|
{
|
||||||
|
if (dev->path.type == DEVICE_PATH_DOMAIN)
|
||||||
|
return "PCI0";
|
||||||
|
|
||||||
|
if (dev->path.type != DEVICE_PATH_PCI || dev->bus->secondary != 0)
|
||||||
|
return NULL;
|
||||||
|
|
||||||
|
switch (dev->path.pci.devfn) {
|
||||||
|
case PCI_DEVFN(0, 0):
|
||||||
|
return "MCHC";
|
||||||
|
}
|
||||||
|
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
/* TODO We could determine how many PCIe busses we need in
|
/* TODO We could determine how many PCIe busses we need in
|
||||||
* the bar. For now that number is hardcoded to a max of 64.
|
* the bar. For now that number is hardcoded to a max of 64.
|
||||||
* See e7525/northbridge.c for an example.
|
* See e7525/northbridge.c for an example.
|
||||||
|
|
@ -84,6 +100,7 @@ static struct device_operations pci_domain_ops = {
|
||||||
.enable_resources = NULL,
|
.enable_resources = NULL,
|
||||||
.init = NULL,
|
.init = NULL,
|
||||||
.scan_bus = pci_domain_scan_bus,
|
.scan_bus = pci_domain_scan_bus,
|
||||||
|
.acpi_name = northbridge_acpi_name,
|
||||||
.write_acpi_tables = northbridge_write_acpi_tables,
|
.write_acpi_tables = northbridge_write_acpi_tables,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -33,6 +33,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
|
||||||
select HAVE_SPI_CONSOLE_SUPPORT
|
select HAVE_SPI_CONSOLE_SUPPORT
|
||||||
select RTC
|
select RTC
|
||||||
select SOUTHBRIDGE_INTEL_COMMON_GPIO if !INTEL_LYNXPOINT_LP
|
select SOUTHBRIDGE_INTEL_COMMON_GPIO if !INTEL_LYNXPOINT_LP
|
||||||
|
select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
|
||||||
select HAVE_INTEL_CHIPSET_LOCKDOWN
|
select HAVE_INTEL_CHIPSET_LOCKDOWN
|
||||||
|
|
||||||
config INTEL_LYNXPOINT_LP
|
config INTEL_LYNXPOINT_LP
|
||||||
|
|
|
||||||
|
|
@ -36,6 +36,7 @@
|
||||||
#include <arch/acpigen.h>
|
#include <arch/acpigen.h>
|
||||||
#include <cbmem.h>
|
#include <cbmem.h>
|
||||||
#include <drivers/intel/gma/i915.h>
|
#include <drivers/intel/gma/i915.h>
|
||||||
|
#include <southbridge/intel/common/acpi_pirq_gen.h>
|
||||||
|
|
||||||
#define NMI_OFF 0
|
#define NMI_OFF 0
|
||||||
|
|
||||||
|
|
@ -789,6 +790,16 @@ static void southbridge_inject_dsdt(struct device *dev)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static const char *lpc_acpi_name(const struct device *dev)
|
||||||
|
{
|
||||||
|
return "LPCB";
|
||||||
|
}
|
||||||
|
|
||||||
|
static void southbridge_fill_ssdt(struct device *dev)
|
||||||
|
{
|
||||||
|
intel_acpi_gen_def_acpi_pirq(dev);
|
||||||
|
}
|
||||||
|
|
||||||
static unsigned long southbridge_write_acpi_tables(struct device *device,
|
static unsigned long southbridge_write_acpi_tables(struct device *device,
|
||||||
unsigned long start,
|
unsigned long start,
|
||||||
struct acpi_rsdp *rsdp)
|
struct acpi_rsdp *rsdp)
|
||||||
|
|
@ -835,7 +846,9 @@ static struct device_operations device_ops = {
|
||||||
.read_resources = pch_lpc_read_resources,
|
.read_resources = pch_lpc_read_resources,
|
||||||
.set_resources = pci_dev_set_resources,
|
.set_resources = pci_dev_set_resources,
|
||||||
.enable_resources = pci_dev_enable_resources,
|
.enable_resources = pci_dev_enable_resources,
|
||||||
|
.acpi_fill_ssdt_generator = southbridge_fill_ssdt,
|
||||||
.acpi_inject_dsdt_generator = southbridge_inject_dsdt,
|
.acpi_inject_dsdt_generator = southbridge_inject_dsdt,
|
||||||
|
.acpi_name = lpc_acpi_name,
|
||||||
.write_acpi_tables = southbridge_write_acpi_tables,
|
.write_acpi_tables = southbridge_write_acpi_tables,
|
||||||
.init = lpc_init,
|
.init = lpc_init,
|
||||||
.enable = pch_lpc_enable,
|
.enable = pch_lpc_enable,
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue