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Replace spaces with tabs. Trivial. 

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5202 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Myles Watson 2010-03-11 22:12:10 +00:00
parent ed15220b87
commit f326e3a4fe
3 changed files with 64 additions and 66 deletions
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4
src/cpu/amd/car/cache_as_ram.inc
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@ -270,8 +270,8 @@ clear_fixed_var_mtrr_out:
#else #else
#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
#endif #endif
movl $REAL_XIP_ROM_BASE, %eax movl $REAL_XIP_ROM_BASE, %eax
orl $MTRR_TYPE_WRBACK, %eax orl $MTRR_TYPE_WRBACK, %eax
wrmsr wrmsr
movl $0x203, %ecx movl $0x203, %ecx

62
src/cpu/amd/car/disable_cache_as_ram.c
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@ -2,45 +2,45 @@
/* be warned, this file will be used other cores and core 0 / node 0 */ /* be warned, this file will be used other cores and core 0 / node 0 */
static inline __attribute__((always_inline)) void disable_cache_as_ram(void) static inline __attribute__((always_inline)) void disable_cache_as_ram(void)
{ {
__asm__ __volatile__ ( __asm__ __volatile__ (
/* We don't need cache as ram for now on */ /* We don't need cache as ram for now on */
/* disable cache */ /* disable cache */
"movl %%cr0, %%eax\n\t" "movl %%cr0, %%eax\n\t"
"orl $(0x1<<30),%%eax\n\t" "orl $(0x1<<30),%%eax\n\t"
"movl %%eax, %%cr0\n\t" "movl %%eax, %%cr0\n\t"
/* clear sth */ /* clear sth */
"movl $0x269, %%ecx\n\t" /* fix4k_c8000*/ "movl $0x269, %%ecx\n\t" /* fix4k_c8000*/
"xorl %%edx, %%edx\n\t" "xorl %%edx, %%edx\n\t"
"xorl %%eax, %%eax\n\t" "xorl %%eax, %%eax\n\t"
"wrmsr\n\t" "wrmsr\n\t"
#if CONFIG_DCACHE_RAM_SIZE > 0x8000 #if CONFIG_DCACHE_RAM_SIZE > 0x8000
"movl $0x268, %%ecx\n\t" /* fix4k_c0000*/ "movl $0x268, %%ecx\n\t" /* fix4k_c0000*/
"wrmsr\n\t" "wrmsr\n\t"
#endif #endif
/* disable fixed mtrr from now on, it will be enabled by coreboot_ram again*/ /* disable fixed mtrr from now on, it will be enabled by coreboot_ram again*/
"movl $0xC0010010, %%ecx\n\t" "movl $0xC0010010, %%ecx\n\t"
// "movl $SYSCFG_MSR, %ecx\n\t" // "movl $SYSCFG_MSR, %ecx\n\t"
"rdmsr\n\t" "rdmsr\n\t"
"andl $(~(3<<18)), %%eax\n\t" "andl $(~(3<<18)), %%eax\n\t"
// "andl $(~(SYSCFG_MSR_MtrrFixDramModEn | SYSCFG_MSR_MtrrFixDramEn)), %eax\n\t" // "andl $(~(SYSCFG_MSR_MtrrFixDramModEn | SYSCFG_MSR_MtrrFixDramEn)), %eax\n\t"
"wrmsr\n\t" "wrmsr\n\t"
/* Set the default memory type and disable fixed and enable variable MTRRs */ /* Set the default memory type and disable fixed and enable variable MTRRs */
"movl $0x2ff, %%ecx\n\t" "movl $0x2ff, %%ecx\n\t"
// "movl $MTRRdefType_MSR, %ecx\n\t" // "movl $MTRRdefType_MSR, %ecx\n\t"
"xorl %%edx, %%edx\n\t" "xorl %%edx, %%edx\n\t"
/* Enable Variable and Disable Fixed MTRRs */ /* Enable Variable and Disable Fixed MTRRs */
"movl $0x00000800, %%eax\n\t" "movl $0x00000800, %%eax\n\t"
"wrmsr\n\t" "wrmsr\n\t"
/* enable cache */ /* enable cache */
"movl %%cr0, %%eax\n\t" "movl %%cr0, %%eax\n\t"
"andl $0x9fffffff,%%eax\n\t" "andl $0x9fffffff,%%eax\n\t"
"movl %%eax, %%cr0\n\t" "movl %%eax, %%cr0\n\t"
::: "memory", "eax", "ecx", "edx" ::: "memory", "eax", "ecx", "edx"
); );
} }
static void disable_cache_as_ram_bsp(void) static void disable_cache_as_ram_bsp(void)

64
src/cpu/amd/car/post_cache_as_ram.c
View File

@ -5,7 +5,7 @@
static inline void print_debug_pcar(const char *strval, uint32_t val) static inline void print_debug_pcar(const char *strval, uint32_t val)
{ {
printk_debug("%s%08x\r\n", strval, val); printk_debug("%s%08x\r\n", strval, val);
} }
/* from linux kernel 2.6.32 asm/string_32.h */ /* from linux kernel 2.6.32 asm/string_32.h */
@ -41,15 +41,15 @@ static void post_cache_as_ram(void)
{ {
#if 1 #if 1
{ {
/* Check value of esp to verify if we have enough rom for stack in Cache as RAM */ /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
unsigned v_esp; unsigned v_esp;
__asm__ volatile ( __asm__ volatile (
"movl %%esp, %0\n\t" "movl %%esp, %0\n\t"
: "=a" (v_esp) : "=a" (v_esp)
); );
print_debug_pcar("v_esp=", v_esp); print_debug_pcar("v_esp=", v_esp);
} }
#endif #endif
unsigned testx = 0x5a5a5a5a; unsigned testx = 0x5a5a5a5a;
@ -59,7 +59,7 @@ static void post_cache_as_ram(void)
ram need to set CONFIG_RAMTOP to 2M and use var mtrr instead. ram need to set CONFIG_RAMTOP to 2M and use var mtrr instead.
*/ */
#if CONFIG_RAMTOP <= 0x100000 #if CONFIG_RAMTOP <= 0x100000
#error "You need to set CONFIG_RAMTOP greater than 1M" #error "You need to set CONFIG_RAMTOP greater than 1M"
#endif #endif
/* So we can access RAM from [1M, CONFIG_RAMTOP) */ /* So we can access RAM from [1M, CONFIG_RAMTOP) */
@ -71,51 +71,49 @@ static void post_cache_as_ram(void)
/* from here don't store more data in CAR */ /* from here don't store more data in CAR */
vErrata343(); vErrata343();
memcopy((void *)((CONFIG_RAMTOP)-CONFIG_DCACHE_RAM_SIZE), (void *)CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); //inline memcopy((void *)((CONFIG_RAMTOP)-CONFIG_DCACHE_RAM_SIZE), (void *)CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); //inline
// dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00); // dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00);
__asm__ volatile ( __asm__ volatile (
/* set new esp */ /* before CONFIG_RAMBASE */ /* set new esp */ /* before CONFIG_RAMBASE */
"subl %0, %%esp\n\t" "subl %0, %%esp\n\t"
::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_RAMTOP) ) ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_RAMTOP) )
/* discard all registers (eax is used for %0), so gcc redo everything /* discard all registers (eax is used for %0), so gcc redo everything
after the stack is moved */ after the stack is moved */
: "cc", "memory", "%ebx", "%ecx", "%edx", "%esi", "%edi", "%ebp" : "cc", "memory", "%ebx", "%ecx", "%edx", "%esi", "%edi", "%ebp"
); );
/* We can put data to stack again */ /* We can put data to stack again */
/* only global variable sysinfo in cache need to be offset */ /* only global variable sysinfo in cache need to be offset */
print_debug("Done\r\n"); print_debug("Done\r\n");
print_debug_pcar("testx = ", testx); print_debug_pcar("testx = ", testx);
print_debug("Disabling cache as ram now \r\n"); print_debug("Disabling cache as ram now \r\n");
disable_cache_as_ram_bsp(); disable_cache_as_ram_bsp();
print_debug("Clearing initial memory region: "); print_debug("Clearing initial memory region: ");
#if CONFIG_HAVE_ACPI_RESUME == 1 #if CONFIG_HAVE_ACPI_RESUME == 1
/* clear only coreboot used region of memory. Note: this may break ECC enabled boards */ /* clear only coreboot used region of memory. Note: this may break ECC enabled boards */
memset((void*) CONFIG_RAMBASE, (CONFIG_RAMTOP) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE, 0); memset((void*) CONFIG_RAMBASE, (CONFIG_RAMTOP) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE, 0);
#else #else
memset((void*)0, ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE), 0); memset((void*)0, ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE), 0);
#endif #endif
print_debug("Done\r\n"); print_debug("Done\r\n");
// dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00); // dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00);
set_sysinfo_in_ram(1); // So other core0 could start to train mem set_sysinfo_in_ram(1); // So other core0 could start to train mem
#if CONFIG_MEM_TRAIN_SEQ == 1 #if CONFIG_MEM_TRAIN_SEQ == 1
// struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
// wait for ap memory to trained // wait for ap memory to trained
// wait_all_core0_mem_trained(sysinfox); // moved to lapic_init_cpus.c // wait_all_core0_mem_trained(sysinfox); // moved to lapic_init_cpus.c
#endif #endif
/*copy and execute coreboot_ram */ /*copy and execute coreboot_ram */
copy_and_run(); copy_and_run();
/* We will not return */ /* We will not return */
print_debug("should not be here -\r\n");
print_debug("should not be here -\r\n");
} }