Replace spaces with tabs. Trivial.
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5202 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -270,8 +270,8 @@ clear_fixed_var_mtrr_out:
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#else
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#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
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#endif
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movl $REAL_XIP_ROM_BASE, %eax
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orl $MTRR_TYPE_WRBACK, %eax
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movl $REAL_XIP_ROM_BASE, %eax
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orl $MTRR_TYPE_WRBACK, %eax
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wrmsr
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movl $0x203, %ecx
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@ -2,45 +2,45 @@
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/* be warned, this file will be used other cores and core 0 / node 0 */
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static inline __attribute__((always_inline)) void disable_cache_as_ram(void)
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{
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__asm__ __volatile__ (
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/* We don't need cache as ram for now on */
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/* disable cache */
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"movl %%cr0, %%eax\n\t"
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"orl $(0x1<<30),%%eax\n\t"
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"movl %%eax, %%cr0\n\t"
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__asm__ __volatile__ (
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/* We don't need cache as ram for now on */
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/* disable cache */
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"movl %%cr0, %%eax\n\t"
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"orl $(0x1<<30),%%eax\n\t"
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"movl %%eax, %%cr0\n\t"
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/* clear sth */
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"movl $0x269, %%ecx\n\t" /* fix4k_c8000*/
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"xorl %%edx, %%edx\n\t"
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"xorl %%eax, %%eax\n\t"
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/* clear sth */
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"movl $0x269, %%ecx\n\t" /* fix4k_c8000*/
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"xorl %%edx, %%edx\n\t"
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"xorl %%eax, %%eax\n\t"
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"wrmsr\n\t"
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#if CONFIG_DCACHE_RAM_SIZE > 0x8000
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"movl $0x268, %%ecx\n\t" /* fix4k_c0000*/
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"wrmsr\n\t"
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"wrmsr\n\t"
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#endif
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/* disable fixed mtrr from now on, it will be enabled by coreboot_ram again*/
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"movl $0xC0010010, %%ecx\n\t"
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// "movl $SYSCFG_MSR, %ecx\n\t"
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"rdmsr\n\t"
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"andl $(~(3<<18)), %%eax\n\t"
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// "andl $(~(SYSCFG_MSR_MtrrFixDramModEn | SYSCFG_MSR_MtrrFixDramEn)), %eax\n\t"
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"wrmsr\n\t"
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/* disable fixed mtrr from now on, it will be enabled by coreboot_ram again*/
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"movl $0xC0010010, %%ecx\n\t"
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// "movl $SYSCFG_MSR, %ecx\n\t"
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"rdmsr\n\t"
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"andl $(~(3<<18)), %%eax\n\t"
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// "andl $(~(SYSCFG_MSR_MtrrFixDramModEn | SYSCFG_MSR_MtrrFixDramEn)), %eax\n\t"
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"wrmsr\n\t"
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/* Set the default memory type and disable fixed and enable variable MTRRs */
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"movl $0x2ff, %%ecx\n\t"
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// "movl $MTRRdefType_MSR, %ecx\n\t"
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"xorl %%edx, %%edx\n\t"
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/* Enable Variable and Disable Fixed MTRRs */
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"movl $0x00000800, %%eax\n\t"
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"wrmsr\n\t"
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/* Set the default memory type and disable fixed and enable variable MTRRs */
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"movl $0x2ff, %%ecx\n\t"
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// "movl $MTRRdefType_MSR, %ecx\n\t"
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"xorl %%edx, %%edx\n\t"
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/* Enable Variable and Disable Fixed MTRRs */
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"movl $0x00000800, %%eax\n\t"
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"wrmsr\n\t"
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/* enable cache */
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"movl %%cr0, %%eax\n\t"
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"andl $0x9fffffff,%%eax\n\t"
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"movl %%eax, %%cr0\n\t"
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::: "memory", "eax", "ecx", "edx"
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);
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/* enable cache */
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"movl %%cr0, %%eax\n\t"
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"andl $0x9fffffff,%%eax\n\t"
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"movl %%eax, %%cr0\n\t"
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::: "memory", "eax", "ecx", "edx"
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);
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}
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static void disable_cache_as_ram_bsp(void)
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@ -5,7 +5,7 @@
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static inline void print_debug_pcar(const char *strval, uint32_t val)
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{
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printk_debug("%s%08x\r\n", strval, val);
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printk_debug("%s%08x\r\n", strval, val);
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}
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/* from linux kernel 2.6.32 asm/string_32.h */
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@ -41,15 +41,15 @@ static void post_cache_as_ram(void)
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{
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#if 1
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{
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/* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
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unsigned v_esp;
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__asm__ volatile (
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"movl %%esp, %0\n\t"
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: "=a" (v_esp)
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);
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print_debug_pcar("v_esp=", v_esp);
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}
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{
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/* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
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unsigned v_esp;
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__asm__ volatile (
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"movl %%esp, %0\n\t"
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: "=a" (v_esp)
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);
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print_debug_pcar("v_esp=", v_esp);
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}
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#endif
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unsigned testx = 0x5a5a5a5a;
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@ -59,7 +59,7 @@ static void post_cache_as_ram(void)
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ram need to set CONFIG_RAMTOP to 2M and use var mtrr instead.
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*/
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#if CONFIG_RAMTOP <= 0x100000
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#error "You need to set CONFIG_RAMTOP greater than 1M"
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#error "You need to set CONFIG_RAMTOP greater than 1M"
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#endif
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/* So we can access RAM from [1M, CONFIG_RAMTOP) */
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@ -71,51 +71,49 @@ static void post_cache_as_ram(void)
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/* from here don't store more data in CAR */
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vErrata343();
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memcopy((void *)((CONFIG_RAMTOP)-CONFIG_DCACHE_RAM_SIZE), (void *)CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); //inline
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// dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00);
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memcopy((void *)((CONFIG_RAMTOP)-CONFIG_DCACHE_RAM_SIZE), (void *)CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); //inline
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// dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00);
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__asm__ volatile (
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/* set new esp */ /* before CONFIG_RAMBASE */
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"subl %0, %%esp\n\t"
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::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_RAMTOP) )
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__asm__ volatile (
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/* set new esp */ /* before CONFIG_RAMBASE */
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"subl %0, %%esp\n\t"
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::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_RAMTOP) )
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/* discard all registers (eax is used for %0), so gcc redo everything
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after the stack is moved */
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: "cc", "memory", "%ebx", "%ecx", "%edx", "%esi", "%edi", "%ebp"
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);
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);
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/* We can put data to stack again */
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/* only global variable sysinfo in cache need to be offset */
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print_debug("Done\r\n");
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print_debug_pcar("testx = ", testx);
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/* only global variable sysinfo in cache need to be offset */
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print_debug("Done\r\n");
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print_debug_pcar("testx = ", testx);
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print_debug("Disabling cache as ram now \r\n");
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disable_cache_as_ram_bsp();
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print_debug("Clearing initial memory region: ");
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print_debug("Clearing initial memory region: ");
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#if CONFIG_HAVE_ACPI_RESUME == 1
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/* clear only coreboot used region of memory. Note: this may break ECC enabled boards */
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memset((void*) CONFIG_RAMBASE, (CONFIG_RAMTOP) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE, 0);
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#else
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memset((void*)0, ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE), 0);
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memset((void*)0, ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE), 0);
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#endif
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print_debug("Done\r\n");
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print_debug("Done\r\n");
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// dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00);
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set_sysinfo_in_ram(1); // So other core0 could start to train mem
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set_sysinfo_in_ram(1); // So other core0 could start to train mem
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#if CONFIG_MEM_TRAIN_SEQ == 1
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// struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
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// wait for ap memory to trained
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// wait_all_core0_mem_trained(sysinfox); // moved to lapic_init_cpus.c
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// wait for ap memory to trained
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// wait_all_core0_mem_trained(sysinfox); // moved to lapic_init_cpus.c
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#endif
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/*copy and execute coreboot_ram */
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copy_and_run();
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/* We will not return */
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print_debug("should not be here -\r\n");
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/*copy and execute coreboot_ram */
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copy_and_run();
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/* We will not return */
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print_debug("should not be here -\r\n");
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}
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