soc/intel/cannonlake: Add bootblock PCH
Add essential initialization needed for PCH in bootblock. Change-Id: I3694e099e78c2989f7192c550cbba098e5df2032 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Andrey Petrov
Aaron Durbin
parent
3e2e0508c2
commit
f35804ba6f
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <device/device.h>
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#include <intelblocks/cse.h>
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#include <intelblocks/fast_spi.h>
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#include <intelblocks/pcr.h>
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#include <intelblocks/rtc.h>
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#include <intelblocks/smbus.h>
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#include <soc/bootblock.h>
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#include <soc/iomap.h>
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#include <soc/lpc.h>
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#include <soc/p2sb.h>
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#include <soc/pci_devs.h>
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#include <soc/pcr_ids.h>
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#include <soc/pmc.h>
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#include <soc/smbus.h>
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#define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x1400
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#define PCR_PSFX_TO_SHDW_BAR0 0
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#define PCR_PSFX_TO_SHDW_BAR1 0x4
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#define PCR_PSFX_TO_SHDW_BAR2 0x8
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#define PCR_PSFX_TO_SHDW_BAR3 0xC
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#define PCR_PSFX_TO_SHDW_BAR4 0x10
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#define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01
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#define PCR_PSFX_T0_SHDW_PCIEN 0x1C
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#define PCR_DMI_LPCLGIR1 0x2730
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#define PCR_DMI_LPCLGIR2 0x2734
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#define PCR_DMI_LPCLGIR3 0x2738
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#define PCR_DMI_LPCLGIR4 0x273c
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#define PCR_DMI_ACPIBA 0x27B4
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#define PCR_DMI_ACPIBDID 0x27B8
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#define PCR_DMI_PMBASEA 0x27AC
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#define PCR_DMI_PMBASEC 0x27B0
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#define PCR_DMI_TCOBASE 0x2778
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#define TCOEN (1 << 1) /* Enable TCO I/O range decode. */
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#define PCR_DMI_LPCIOD 0x2770
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#define PCR_DMI_LPCIOE 0x2774
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static void enable_p2sbbar(void)
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{
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device_t dev = PCH_DEV_P2SB;
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/* Enable PCR Base address in PCH */
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pci_write_config32(dev, PCI_BASE_ADDRESS_0, CONFIG_PCR_BASE_ADDRESS);
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/* Enable P2SB MSE */
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pci_write_config8(dev, PCI_COMMAND,
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PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
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/*
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* Enable decoding for HPET memory address range.
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* HPTC_OFFSET(0x60) bit 7, when set the P2SB will decode
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* the High Performance Timer memory address range
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* selected by bits 1:0
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*/
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pci_write_config8(dev, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT);
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}
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static void soc_config_pwrmbase(void)
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{
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uint32_t reg32;
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/* Assign Resources to PWRMBASE */
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/* Clear BIT 1-2 Command Register */
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reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND);
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reg32 &= ~(PCI_COMMAND_MEMORY);
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pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32);
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/* Program PWRM Base */
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pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS);
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/* Enable Bus Master and MMIO Space */
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reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND);
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reg32 |= PCI_COMMAND_MEMORY;
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pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32);
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/* Enable PWRM in PMC */
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reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL));
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write32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL), reg32 | PWRM_EN);
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}
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void bootblock_pch_early_init(void)
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{
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fast_spi_early_init(SPI_BASE_ADDRESS);
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enable_p2sbbar();
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/*
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* Enabling PWRM Base for accessing
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* Global Reset Cause Register.
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*/
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soc_config_pwrmbase();
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}
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static void soc_config_acpibase(void)
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{
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uint32_t pmc_reg_value;
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pmc_reg_value = pcr_read32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE +
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PCR_PSFX_TO_SHDW_BAR4);
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if (pmc_reg_value != 0xFFFFFFFF)
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{
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/* Disable Io Space before changing the address */
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pcr_rmw32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE +
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PCR_PSFX_T0_SHDW_PCIEN,
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~PCR_PSFX_TO_SHDW_PCIEN_IOEN, 0);
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/* Program ABASE in PSF3 PMC space BAR4*/
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pcr_write32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE +
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PCR_PSFX_TO_SHDW_BAR4,
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ACPI_BASE_ADDRESS);
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/* Enable IO Space */
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pcr_rmw32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE +
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PCR_PSFX_T0_SHDW_PCIEN,
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~0, PCR_PSFX_TO_SHDW_PCIEN_IOEN);
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}
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}
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static void soc_config_tco(void)
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{
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uint32_t reg32;
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uint16_t tcobase;
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uint16_t tcocnt;
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/* Disable TCO in SMBUS Device first before changing Base Address */
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reg32 = pci_read_config32(PCH_DEV_SMBUS, TCOCTL);
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reg32 &= ~TCO_EN;
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pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32);
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/* Program TCO Base */
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tcobase = TCO_BASE_ADDRESS;
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pci_write_config32(PCH_DEV_SMBUS, TCOBASE, tcobase);
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/* Enable TCO in SMBUS */
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pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32 | TCO_BASE_EN);
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/*
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* Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1]
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*/
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pcr_write32(PID_DMI, PCR_DMI_TCOBASE, tcobase | TCOEN);
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/* Program TCO timer halt */
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tcocnt = inw(tcobase + TCO1_CNT);
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tcocnt |= TCO_TMR_HLT;
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outw(tcocnt, tcobase + TCO1_CNT);
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}
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void pch_early_iorange_init(void)
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{
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uint16_t dec_rng, dec_en = 0;
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/* IO Decode Range */
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if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO) &&
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IS_ENABLED(CONFIG_UART_DEBUG)) {
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dec_rng = COMA_RANGE | (COMB_RANGE << 4);
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dec_en = COMA_LPC_EN | COMB_LPC_EN;
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pci_write_config16(PCH_DEV_LPC, LPC_IO_DEC, dec_rng);
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pcr_write16(PID_DMI, PCR_DMI_LPCIOD, dec_rng);
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}
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/* IO Decode Enable */
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dec_en |= SE_LPC_EN | KBC_LPC_EN | MC1_LPC_EN;
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pci_write_config16(PCH_DEV_LPC, LPC_EN, dec_en);
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pcr_write16(PID_DMI, PCR_DMI_LPCIOE, dec_en);
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}
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void pch_early_init(void)
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{
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/*
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* Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT,
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* GPE0_STS, GPE0_EN registers.
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*/
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soc_config_acpibase();
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/* Programming TCO_BASE_ADDRESS and TCO Timer Halt */
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soc_config_tco();
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/* Program SMBUS_BASE_ADDRESS and Enable it */
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smbus_common_init();
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enable_rtc_upper_bank();
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heci_init(HECI1_BASE_ADDRESS);
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}
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@ -0,0 +1,55 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _SOC_CANNONLAKE_LPC_H_
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#define _SOC_CANNONLAKE_LPC_H_
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/* PCI Configuration Space (D31:F0): LPC */
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#define SCI_IRQ_SEL (7 << 0)
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#define SCIS_IRQ9 0
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#define SCIS_IRQ10 1
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#define SCIS_IRQ11 2
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#define SCIS_IRQ20 4
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#define SCIS_IRQ21 5
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#define SCIS_IRQ22 6
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#define SCIS_IRQ23 7
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#define SERIRQ_CNTL 0x64
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#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */
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#define COMA_RANGE 0x0 /* 0x3F8 - 0x3FF COM1*/
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#define COMB_RANGE 0x1 /* 0x2F8 - 0x2FF COM2*/
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#define LPC_EN 0x82 /* LPC IF Enables Register */
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#define MC2_LPC_EN (1 << 13) /* 0x4e/0x4f */
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#define SE_LPC_EN (1 << 12) /* 0x2e/0x2f */
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#define MC1_LPC_EN (1 << 11) /* 0x62/0x66 */
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#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */
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#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */
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#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */
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#define FDD_LPC_EN (1 << 3) /* Floppy Drive Enable */
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#define LPT_LPC_EN (1 << 2) /* Parallel Port Enable */
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#define COMB_LPC_EN (1 << 1) /* Com Port B Enable */
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#define COMA_LPC_EN (1 << 0) /* Com Port A Enable */
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#define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */
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#define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */
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#define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */
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#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */
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#define LGMR 0x98 /* LPC Generic Memory Range */
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#define BIOS_CNTL 0xdc
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#define LPC_BC_BILD (1 << 7) /* BILD */
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#define LPC_BC_LE (1 << 2) /* LE */
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#define LPC_BC_EISS (1 << 5) /* EISS */
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#define PCCTL 0xE0 /* PCI Clock Control */
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#define CLKRUN_EN (1 << 0)
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#endif
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@ -0,0 +1,27 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _SOC_CANNONLAKE_P2SB_H_
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#define _SOC_CANNONLAKE_P2SB_H_
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#define HPTC_OFFSET 0x60
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#define HPTC_ADDR_ENABLE_BIT (1 << 7)
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#define PCH_P2SB_EPMASK0 0x220
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#define PCH_P2SB_EPMASK(mask_number) (PCH_P2SB_EPMASK0 + (mask_number * 4))
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#define PCH_P2SB_E0 0xE0
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#endif
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@ -0,0 +1,32 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _SOC_CANNONLAKE_PCH_H_
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#define _SOC_CANNONLAKE_PCH_H_
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#include <stdint.h>
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#define PCH_H 1
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#define PCH_LP 2
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#define PCH_UNKNOWN_SERIES 0xFF
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u8 pch_revision(void);
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u16 pch_type(void);
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void pch_log_state(void);
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void pch_uart_init(void);
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#endif
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@ -0,0 +1,38 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (c) 2017 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef SOC_CANNONLAKE_PCR_H
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#define SOC_CANNONLAKE_PCR_H
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/*
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* Port ids
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*/
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#define PID_GPIOCOM4 0x6a
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#define PID_GPIOCOM3 0x6b
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#define PID_GPIOCOM2 0x6c
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#define PID_GPIOCOM1 0x6d
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#define PID_GPIOCOM0 0x6e
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#define PID_DMI 0x88
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#define PID_PSTH 0x89
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#define PID_PSF1 0xba
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#define PID_PSF2 0xbb
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#define PID_PSF3 0xbc
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#define PID_PSF4 0xbd
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#define PID_SCS 0xc0
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#define PID_RTC 0xc3
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#define PID_ITSS 0xc2
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#define PID_LPC 0xc7
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#define PID_SERIALIO 0xcb
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#endif
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2005 Yinghai Lu <yinghailu@gmail.com>
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* Copyright (C) 2009 coresystems GmbH
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
|
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* the Free Software Foundation; version 2 of the License.
|
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
|
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*/
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#ifndef _SOC_CANNONLAKE_SMBUS_H_
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#define _SOC_CANNONLAKE_SMBUS_H_
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/* PCI registers */
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#define TCOBASE 0x50 /* TCO base address. */
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#define TCOCTL 0x54
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#define TCO_BASE_EN (1 << 8) /* TCO base enable. */
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/* IO and MMIO registers under primary BAR */
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/* Set address for PCH as SMBus slave role */
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#define SMB_RCV_SLVA 0x09
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/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
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#define TCO1_STS 0x04
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#define TCO2_STS 0x06
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#define TCO2_STS_SECOND_TO 0x02
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#define TCO2_STS_BOOT 0x04
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#define TCO1_CNT 0x08
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#define TCO_LOCK (1 << 12)
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#define TCO_TMR_HLT (1 << 11)
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/*
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* Default slave address value for PCH. This value is set to match default
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* value set by hardware. It is useful since PCH is able to respond even
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* before CPU is up. This is reset by RSMRST# but not by PLTRST#.
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*/
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#define SMBUS_SLAVE_ADDR 0x44
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#endif
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@ -0,0 +1,104 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2008 coresystems GmbH
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* Copyright (C) 2014 Google Inc.
|
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* Copyright (C) 2017 Intel Corporation.
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*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
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||||
#ifndef SOC_CANNONLAKE_SYSTEMAGENT_H
|
||||
#define SOC_CANNONLAKE_SYSTEMAGENT_H
|
||||
|
||||
#include <intelblocks/systemagent.h>
|
||||
#include <soc/iomap.h>
|
||||
|
||||
/* Device 0:0.0 PCI configuration space */
|
||||
|
||||
#define EPBAR 0x40
|
||||
#define PCIEXBAR 0x60
|
||||
#define DMIBAR 0x68
|
||||
#define GGC 0x50 /* GMCH Graphics Control */
|
||||
#define DEVEN 0x54 /* Device Enable */
|
||||
#define DEVEN_D7EN (1 << 14)
|
||||
#define DEVEN_D4EN (1 << 7)
|
||||
#define DEVEN_D3EN (1 << 5)
|
||||
#define DEVEN_D2EN (1 << 4)
|
||||
#define DEVEN_D1F0EN (1 << 3)
|
||||
#define DEVEN_D1F1EN (1 << 2)
|
||||
#define DEVEN_D1F2EN (1 << 1)
|
||||
#define DEVEN_D0EN (1 << 0)
|
||||
#define DPR 0x5c
|
||||
#define DPR_EPM (1 << 2)
|
||||
#define DPR_PRS (1 << 1)
|
||||
#define DPR_SIZE_MASK 0xff0
|
||||
|
||||
#define PAM0 0x80
|
||||
#define PAM1 0x81
|
||||
#define PAM2 0x82
|
||||
#define PAM3 0x83
|
||||
#define PAM4 0x84
|
||||
#define PAM5 0x85
|
||||
#define PAM6 0x86
|
||||
|
||||
#define SMRAM 0x88 /* System Management RAM Control */
|
||||
#define D_OPEN (1 << 6)
|
||||
#define D_CLS (1 << 5)
|
||||
#define D_LCK (1 << 4)
|
||||
#define G_SMRAME (1 << 3)
|
||||
#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
|
||||
|
||||
#define MESEG_BASE 0x70 /* Management Engine Base. */
|
||||
#define MESEG_LIMIT 0x78 /* Management Engine Limit. */
|
||||
#define TOM 0xa0 /* Top of DRAM in memory controller space. */
|
||||
#define SKPAD 0xdc /* Scratchpad Data */
|
||||
|
||||
/* MCHBAR */
|
||||
|
||||
#define MCHBAR8(x) (*(volatile u8 *)(MCH_BASE_ADDRESS + x))
|
||||
#define MCHBAR16(x) (*(volatile u16 *)(MCH_BASE_ADDRESS + x))
|
||||
#define MCHBAR32(x) (*(volatile u32 *)(MCH_BASE_ADDRESS + x))
|
||||
|
||||
#define MCHBAR_PEI_VERSION 0x5034
|
||||
#define REMAPBASE 0x5090 /* Remap base. */
|
||||
#define REMAPLIMIT 0x5098 /* Remap limit. */
|
||||
#define BIOS_RESET_CPL 0x5da8
|
||||
#define EDRAMBAR 0x5408
|
||||
#define MCH_PAIR 0x5418
|
||||
#define REGBAR 0x5420
|
||||
|
||||
#define MCH_PKG_POWER_LIMIT_LO 0x59a0
|
||||
#define MCH_PKG_POWER_LIMIT_HI 0x59a4
|
||||
#define MCH_DDR_POWER_LIMIT_LO 0x58e0
|
||||
#define MCH_DDR_POWER_LIMIT_HI 0x58e4
|
||||
|
||||
/* PCODE MMIO communications live in the MCHBAR. */
|
||||
#define BIOS_MAILBOX_INTERFACE 0x5da4
|
||||
#define MAILBOX_RUN_BUSY (1 << 31)
|
||||
/* Errors are returned back in bits 7:0. */
|
||||
#define MAILBOX_BIOS_ERROR_NONE 0
|
||||
#define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1
|
||||
#define MAILBOX_BIOS_ERROR_TIMEOUT 2
|
||||
#define MAILBOX_BIOS_ERROR_ILLEGAL_DATA 3
|
||||
#define MAILBOX_BIOS_ERROR_RESERVED 4
|
||||
#define MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID 5
|
||||
#define MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED 6
|
||||
#define MAILBOX_BIOS_ERROR_VR_ERROR 7
|
||||
/* Data is passed through bits 31:0 of the data register. */
|
||||
#define BIOS_MAILBOX_DATA 0x5da0
|
||||
|
||||
/* System Agent identification */
|
||||
u8 systemagent_revision(void);
|
||||
|
||||
/* Top of 32bit usable memory */
|
||||
u32 top_of_32bit_ram(void);
|
||||
|
||||
#endif
|
||||
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Reference in New Issue