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Revert "sb/intel/i82801gx: Use "sb/intel/common/tco.h" macros" 

This reverts commit 9f0e21a4da.

It should be allowed for i82801gx/early_init.c to have
   #include <southbridge/intel/common/pmutil.h>

But there is a conflict:

src/southbridge/intel/common/pmutil.h:
   #define TCO1_CNT  0x68
src/southbridge/intel/common/tco.h:
   #define TCO1_CNT  0x08

Followup works resolve the difficulties around the offset
0x60 used for TCO register bank, tree-wide.

Change-Id: I827558a0e0ef1c4d1f866756df51cd1b2abfc7a0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Kyösti Mälkki 2022-11-25 06:22:10 +02:00
parent 5b92aa9c64
commit f38f30a3de
3 changed files with 8 additions and 7 deletions
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9
src/southbridge/intel/i82801gx/early_init.c
View File

@ -6,7 +6,6 @@
#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/gpio.h>
#include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/pmbase.h>
#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/common/tco.h>
#include "chip.h" #include "chip.h"
#include "i82801gx.h" #include "i82801gx.h"
@ -58,6 +57,8 @@ void i82801gx_setup_bars(void)
pci_write_config8(d31f0, GPIO_CNTL, GPIO_EN); pci_write_config8(d31f0, GPIO_CNTL, GPIO_EN);
} }
#define TCO_BASE 0x60
#if ENV_RAMINIT #if ENV_RAMINIT
void i82801gx_early_init(void) void i82801gx_early_init(void)
{ {
@ -71,9 +72,9 @@ void i82801gx_early_init(void)
printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); printk(BIOS_DEBUG, "Disabling Watchdog reboot...");
RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */
write_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT, TCO_TMR_HLT); write_pmbase16(TCO_BASE + 0x8, (1 << 11)); /* halt timer */
write_pmbase16(PMBASE_TCO_OFFSET + TCO1_STS, TCO1_TIMEOUT); write_pmbase16(TCO_BASE + 0x4, (1 << 3)); /* clear timeout */
write_pmbase16(PMBASE_TCO_OFFSET + TCO2_STS, SECOND_TO_STS); write_pmbase16(TCO_BASE + 0x6, (1 << 1)); /* clear 2nd timeout */
printk(BIOS_DEBUG, " done.\n"); printk(BIOS_DEBUG, " done.\n");
/* program secondary mlt XXX byte? */ /* program secondary mlt XXX byte? */

1
src/southbridge/intel/i82801gx/i82801gx.h
View File

@ -323,6 +323,7 @@ void ich7_setup_cir(void);
#define DEVACT_STS 0x44 #define DEVACT_STS 0x44
#define SS_CNT 0x50 #define SS_CNT 0x50
#define C3_RES 0x54 #define C3_RES 0x54
#define TCO1_CNT 0x68
#endif /* __ACPI__ */ #endif /* __ACPI__ */
#endif /* SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H */ #endif /* SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H */

5
src/southbridge/intel/i82801gx/lpc.c
View File

@ -20,7 +20,6 @@
#include <southbridge/intel/common/hpet.h> #include <southbridge/intel/common/hpet.h>
#include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/pmbase.h>
#include <southbridge/intel/common/spi.h> #include <southbridge/intel/common/spi.h>
#include <southbridge/intel/common/tco.h>
#include "chip.h" #include "chip.h"
#include "i82801gx.h" #include "i82801gx.h"
@ -428,9 +427,9 @@ static void lpc_final(struct device *dev)
pci_or_config16(dev, GEN_PMCON_1, 1 << 4); pci_or_config16(dev, GEN_PMCON_1, 1 << 4);
/* TCO_Lock */ /* TCO_Lock */
tco1_cnt = read_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT); tco1_cnt = inw(DEFAULT_PMBASE + 0x60 + TCO1_CNT);
tco1_cnt |= (1 << 12); /* TCO lock */ tco1_cnt |= (1 << 12); /* TCO lock */
write_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT, tco1_cnt); outw(tco1_cnt, DEFAULT_PMBASE + 0x60 + TCO1_CNT);
/* Indicate finalize step with post code */ /* Indicate finalize step with post code */
post_code(POST_OS_BOOT); post_code(POST_OS_BOOT);