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buildgcc: Integrate nds32 update from Andes Technology 

This patch has been provided by Mentor Chih-Chyang Chang
on behalf of Andes Technology. It fixes using the coreboot
toolchain to compile the Chrome EC code base on the ITE8320
embedded controller.

The new patch incorporates a fix for the issue previously
fixed by patches/gcc-6.3.0_nds32.patch, so that patch can
be removed.

patches/gcc-6.3.0_riscv.patch needs to be slightly adjusted
to still apply cleanly (configure scripts only).

Change-Id: I0033888360f13ba951b692b3242aab6697ca61b3
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Stefan Reinauer 2017-08-07 15:27:15 -07:00 committed by Patrick Georgi
parent d37ebddfd8
commit f3e23a3135
4 changed files with 73403 additions and 23 deletions
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4
util/crossgcc/buildgcc
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@ -18,8 +18,8 @@
cd $(dirname $0)
CROSSGCC_DATE="July 27th, 2017"
CROSSGCC_VERSION="1.46"
CROSSGCC_DATE="August 16th, 2017"
CROSSGCC_VERSION="1.47"
CROSSGCC_COMMIT=$( git describe )
# default settings

17
util/crossgcc/patches/gcc-6.3.0_nds32.patch
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@ -1,17 +0,0 @@
diff -urN gcc-6.1.0.orig/gcc/config/nds32/nds32.md gcc-6.1.0/gcc/config/nds32/nds32.md
--- gcc-6.1.0.orig/gcc/config/nds32/nds32.md 2015-01-15 22:45:09.000000000 -0800
+++ gcc-6.1.0/gcc/config/nds32/nds32.md 2016-04-14 22:09:09.000000000 -0700
@@ -2289,11 +2289,11 @@
emit_jump_insn (gen_cbranchsi4 (test, operands[0], operands[2],
operands[4]));
- operands[5] = gen_reg_rtx (SImode);
+ rtx tmp = gen_reg_rtx (SImode);
/* Step C, D, E, and F, using another temporary register operands[5]. */
emit_jump_insn (gen_casesi_internal (operands[0],
operands[3],
- operands[5]));
+ tmp));
DONE;
})

73397
util/crossgcc/patches/gcc-6.3.0_nds32_ite.patch Normal file
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File diff suppressed because it is too large Load Diff

8
util/crossgcc/patches/gcc-6.3.0_riscv.patch
View File

@ -9030,9 +9030,9 @@ index c9e43fb80e3..5359a4e6ee5 100755
# version to the per-target configury.
case "$cpu_type" in
aarch64 | alpha | arm | avr | bfin | cris | i386 | m32c | m68k | microblaze \
- | mips | nios2 | pa | rs6000 | score | sparc | spu | tilegx | tilepro \
- | mips | nds32 | nios2 | pa | rs6000 | score | sparc | spu | tilegx | tilepro \
- | visium | xstormy16 | xtensa)
+ | mips | nios2 | pa | riscv | rs6000 | score | sparc | spu | tilegx \
+ | mips | nds32 | nios2 | pa | riscv | rs6000 | score | sparc | spu | tilegx \
+ | tilepro | visium | xstormy16 | xtensa)
insn="nop"
;;
@ -9063,9 +9063,9 @@ index 33f9a0ecdc6..673fb1bb891 100644
# version to the per-target configury.
case "$cpu_type" in
aarch64 | alpha | arm | avr | bfin | cris | i386 | m32c | m68k | microblaze \
- | mips | nios2 | pa | rs6000 | score | sparc | spu | tilegx | tilepro \
- | mips | nds32 | nios2 | pa | rs6000 | score | sparc | spu | tilegx | tilepro \
- | visium | xstormy16 | xtensa)
+ | mips | nios2 | pa | riscv | rs6000 | score | sparc | spu | tilegx \
+ | mips | nds32 | nios2 | pa | riscv | rs6000 | score | sparc | spu | tilegx \
+ | tilepro | visium | xstormy16 | xtensa)
insn="nop"
;;