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cpu/intel/slot_1: Increase CAR size to 8KiB 

Because cpu/intel/car/romstage.c assumes a 8KiB stack size
when setting up stack guards, and all Slot 1 compatible
CPUs have enough L1 cache available for the increase.

Adjust DCACHE_RAM_BASE to match.

Boot tested on asus/p2b-ls and asus/p3b-f using a 1400MHz
Tualeron. The latter actually requires this patch to boot
successfully.

Change-Id: I5b440e7be4f3149378db88872872012c92049c20
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Keith Hui 2017-09-02 17:59:41 -04:00 committed by Kyösti Mälkki
parent 0a9982f3fb
commit f3ec5ed555
1 changed files with 2 additions and 2 deletions
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4
src/cpu/intel/slot_1/Kconfig
View File

@ -28,10 +28,10 @@ config SLOT_SPECIFIC_OPTIONS # dummy
config DCACHE_RAM_BASE
hex
default 0xcf000
default 0xce000
config DCACHE_RAM_SIZE
hex
default 0x01000
default 0x02000
endif