soc/amd/cezanne,picasso,sabrina/smihandler: add comment about SMN access

The SMI sleep entry handler will access the SMN space via the index/data
register at PCI config space offsets 0xb8 and 0xbc of the device at bus
0, device 0, function 0. This register pair is also used by other
software components running on the x86 cores after boot, so it should be
saved and restored at the beginning/end of the SMI handler if it
accesses SMN. The sleep entry SMI handler is a special case, since the
OS is already done at the moment we enter the sleep SMI handler which is
the last code that gets run on the x86 cores before entering S3/4/5.

BUG=b:237004699

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0980562ef8a61489082a81c71d6d00d0786d68cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65529
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>

src/soc/amd/cezanne/smihandler.c

@@ -47,6 +47,11 @@ static void fch_apmc_smi_handler(void)
 	mainboard_smi_apmc(cmd);
 }
 
+/*
+ * Both the psp_notify_sx_info and the smu_sx_entry call will clobber the SMN index register
+ * during the SMN accesses. Since the SMI handler is the last thing that gets called before
+ * entering S3, this won't interfere with any indirect SMN accesses via the same register pair.
+ */
 static void fch_slp_typ_handler(void)
 {
 	uint32_t pci_ctrl, reg32;

src/soc/amd/mendocino/smihandler.c

@@ -47,6 +47,11 @@ static void fch_apmc_smi_handler(void)
 	mainboard_smi_apmc(cmd);
 }
 
+/*
+ * Both the psp_notify_sx_info and the smu_sx_entry call will clobber the SMN index register
+ * during the SMN accesses. Since the SMI handler is the last thing that gets called before
+ * entering S3, this won't interfere with any indirect SMN accesses via the same register pair.
+ */
 static void fch_slp_typ_handler(void)
 {
 	uint32_t pci_ctrl, reg32;

src/soc/amd/picasso/smihandler.c

@@ -45,6 +45,11 @@ static void fch_apmc_smi_handler(void)
 	mainboard_smi_apmc(cmd);
 }
 
+/*
+ * Both the psp_notify_sx_info and the smu_sx_entry call will clobber the SMN index register
+ * during the SMN accesses. Since the SMI handler is the last thing that gets called before
+ * entering S3, this won't interfere with any indirect SMN accesses via the same register pair.
+ */
 static void fch_slp_typ_handler(void)
 {
 	uint32_t pci_ctrl, reg32;