GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

google/veyron*: change .ddrconfig from 14 to 3 

There are two configs, sdram-lpddr3-hynix-2GB.inc and
sdram-lpddr3-samsung-2GB-24EB.inc that use .ddrconfig = 14.

Changing .ddrconfig from 14 to 3 improves performance
especially on contiguous memory accesses. Comparing the .ddrconfig:
 - if .ddrconfig = 3,
   C RDRR RRRR RRRR RRRR RBBB CCCC CCCC C---
 - if .ddrconfig = 14,
   C DRBB BRRR RRRR RRRR RRRR CCCC CCCC C---
where
 - R: indicates Row bits
 - B: indicates Bank bits
 - C: indicates Column bits
 - D: indicates Chip selects bits

.ddrconfig = 3 has multiple banks switching which improves DDR timing.

BUG=chrome-os-partner:57321
TEST=Boot from fievel and play video
BRANCH=veyron

Change-Id: Ifdcedc28e84429b8b79c7553b38b667631d29c09
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 93882e4f2000d93c9dae5e6d4b2e1f4b7bc9489e
Original-Change-Id: Ic98ebae48609a7604ec678b6bd14dd2b29b669c4
Original-Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/404691
Original-Commit-Ready: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17210
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
ZhengShunQian 2016-10-28 16:16:04 +08:00 committed by Patrick Georgi
parent 8859afdb44
commit f4401eb997
12 changed files with 12 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-hynix-2GB.inc
View File

@ -69,7 +69,7 @@
}, },
.noc_timing = 0x20D266A4, .noc_timing = 0x20D266A4,
.noc_activate = 0x5B6, .noc_activate = 0x5B6,
.ddrconfig = 14, .ddrconfig = 3,
.ddr_freq = 533*MHz, .ddr_freq = 533*MHz,
.dramtype = LPDDR3, .dramtype = LPDDR3,
.num_channels = 2, .num_channels = 2,

2
src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc
View File

@ -69,7 +69,7 @@
}, },
.noc_timing = 0x20D266A4, .noc_timing = 0x20D266A4,
.noc_activate = 0x5B6, .noc_activate = 0x5B6,
.ddrconfig = 14, .ddrconfig = 3,
.ddr_freq = 533*MHz, .ddr_freq = 533*MHz,
.dramtype = LPDDR3, .dramtype = LPDDR3,
.num_channels = 2, .num_channels = 2,

2
src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-hynix-2GB.inc
View File

@ -69,7 +69,7 @@
}, },
.noc_timing = 0x20D266A4, .noc_timing = 0x20D266A4,
.noc_activate = 0x5B6, .noc_activate = 0x5B6,
.ddrconfig = 14, .ddrconfig = 3,
.ddr_freq = 533*MHz, .ddr_freq = 533*MHz,
.dramtype = LPDDR3, .dramtype = LPDDR3,
.num_channels = 2, .num_channels = 2,

2
src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc
View File

@ -69,7 +69,7 @@
}, },
.noc_timing = 0x20D266A4, .noc_timing = 0x20D266A4,
.noc_activate = 0x5B6, .noc_activate = 0x5B6,
.ddrconfig = 14, .ddrconfig = 3,
.ddr_freq = 533*MHz, .ddr_freq = 533*MHz,
.dramtype = LPDDR3, .dramtype = LPDDR3,
.num_channels = 2, .num_channels = 2,

2
src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-hynix-2GB.inc
View File

@ -69,7 +69,7 @@
}, },
.noc_timing = 0x20D266A4, .noc_timing = 0x20D266A4,
.noc_activate = 0x5B6, .noc_activate = 0x5B6,
.ddrconfig = 14, .ddrconfig = 3,
.ddr_freq = 533*MHz, .ddr_freq = 533*MHz,
.dramtype = LPDDR3, .dramtype = LPDDR3,
.num_channels = 2, .num_channels = 2,

2
src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc
View File

@ -69,7 +69,7 @@
}, },
.noc_timing = 0x20D266A4, .noc_timing = 0x20D266A4,
.noc_activate = 0x5B6, .noc_activate = 0x5B6,
.ddrconfig = 14, .ddrconfig = 3,
.ddr_freq = 533*MHz, .ddr_freq = 533*MHz,
.dramtype = LPDDR3, .dramtype = LPDDR3,
.num_channels = 2, .num_channels = 2,

2
src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-hynix-2GB.inc
View File

@ -69,7 +69,7 @@
}, },
.noc_timing = 0x20D266A4, .noc_timing = 0x20D266A4,
.noc_activate = 0x5B6, .noc_activate = 0x5B6,
.ddrconfig = 14, .ddrconfig = 3,
.ddr_freq = 533*MHz, .ddr_freq = 533*MHz,
.dramtype = LPDDR3, .dramtype = LPDDR3,
.num_channels = 2, .num_channels = 2,

2
src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc
View File

@ -69,7 +69,7 @@
}, },
.noc_timing = 0x20D266A4, .noc_timing = 0x20D266A4,
.noc_activate = 0x5B6, .noc_activate = 0x5B6,
.ddrconfig = 14, .ddrconfig = 3,
.ddr_freq = 533*MHz, .ddr_freq = 533*MHz,
.dramtype = LPDDR3, .dramtype = LPDDR3,
.num_channels = 2, .num_channels = 2,

2
src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-hynix-2GB.inc
View File

@ -70,7 +70,7 @@
}, },
.noc_timing = 0x20D266A4, .noc_timing = 0x20D266A4,
.noc_activate = 0x5B6, .noc_activate = 0x5B6,
.ddrconfig = 14, .ddrconfig = 3,
.ddr_freq = 533*MHz, .ddr_freq = 533*MHz,
.dramtype = LPDDR3, .dramtype = LPDDR3,
.num_channels = 2, .num_channels = 2,

2
src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc
View File

@ -69,7 +69,7 @@
}, },
.noc_timing = 0x20D266A4, .noc_timing = 0x20D266A4,
.noc_activate = 0x5B6, .noc_activate = 0x5B6,
.ddrconfig = 14, .ddrconfig = 3,
.ddr_freq = 533*MHz, .ddr_freq = 533*MHz,
.dramtype = LPDDR3, .dramtype = LPDDR3,
.num_channels = 2, .num_channels = 2,

2
src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-hynix-2GB.inc
View File

@ -69,7 +69,7 @@
}, },
.noc_timing = 0x20D266A4, .noc_timing = 0x20D266A4,
.noc_activate = 0x5B6, .noc_activate = 0x5B6,
.ddrconfig = 14, .ddrconfig = 3,
.ddr_freq = 533*MHz, .ddr_freq = 533*MHz,
.dramtype = LPDDR3, .dramtype = LPDDR3,
.num_channels = 2, .num_channels = 2,

2
src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc
View File

@ -69,7 +69,7 @@
}, },
.noc_timing = 0x20D266A4, .noc_timing = 0x20D266A4,
.noc_activate = 0x5B6, .noc_activate = 0x5B6,
.ddrconfig = 14, .ddrconfig = 3,
.ddr_freq = 533*MHz, .ddr_freq = 533*MHz,
.dramtype = LPDDR3, .dramtype = LPDDR3,
.num_channels = 2, .num_channels = 2,