No description
f4401eb997
There are two configs, sdram-lpddr3-hynix-2GB.inc and sdram-lpddr3-samsung-2GB-24EB.inc that use .ddrconfig = 14. Changing .ddrconfig from 14 to 3 improves performance especially on contiguous memory accesses. Comparing the .ddrconfig: - if .ddrconfig = 3, C RDRR RRRR RRRR RRRR RBBB CCCC CCCC C--- - if .ddrconfig = 14, C DRBB BRRR RRRR RRRR RRRR CCCC CCCC C--- where - R: indicates Row bits - B: indicates Bank bits - C: indicates Column bits - D: indicates Chip selects bits .ddrconfig = 3 has multiple banks switching which improves DDR timing. BUG=chrome-os-partner:57321 TEST=Boot from fievel and play video BRANCH=veyron Change-Id: Ifdcedc28e84429b8b79c7553b38b667631d29c09 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 93882e4f2000d93c9dae5e6d4b2e1f4b7bc9489e Original-Change-Id: Ic98ebae48609a7604ec678b6bd14dd2b29b669c4 Original-Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/404691 Original-Commit-Ready: Shunqian Zheng <zhengsq@rock-chips.com> Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17210 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> |
||
---|---|---|
3rdparty | ||
Documentation | ||
payloads | ||
src | ||
util | ||
.checkpatch.conf | ||
.clang-format | ||
.gitignore | ||
.gitmodules | ||
.gitreview | ||
COPYING | ||
gnat.adc | ||
MAINTAINERS | ||
Makefile | ||
Makefile.inc | ||
README | ||
toolchain.inc |
------------------------------------------------------------------------------- coreboot README ------------------------------------------------------------------------------- coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload. With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required. coreboot was formerly known as LinuxBIOS. Payloads -------- After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot. See http://www.coreboot.org/Payloads for a list of supported payloads. Supported Hardware ------------------ coreboot supports a wide range of chipsets, devices, and mainboards. For details please consult: * http://www.coreboot.org/Supported_Motherboards * http://www.coreboot.org/Supported_Chipsets_and_Devices Build Requirements ------------------ * make * gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case). * iasl (for targets with ACPI support) Optional: * doxygen (for generating/viewing documentation) * gdb (for better debugging facilities on some targets) * ncurses (for 'make menuconfig' and 'make nconfig') * flex and bison (for regenerating parsers) Building coreboot ----------------- Please consult http://www.coreboot.org/Build_HOWTO for details. Testing coreboot Without Modifying Your Hardware ------------------------------------------------ If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU. Please see http://www.coreboot.org/QEMU for details. Website and Mailing List ------------------------ Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website: http://www.coreboot.org You can contact us directly on the coreboot mailing list: http://www.coreboot.org/Mailinglist Copyright and License --------------------- The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details. coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details. This makes the resulting coreboot images licensed under the GPL, version 2.