nb/intel/haswell: Calculate TSEG limit from registers
Done for consistency with other northbridges. Change-Id: I08023809477c1cef0d7762b5e4fde65fadf6a6d8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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1 changed files with 6 additions and 4 deletions
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@ -4,13 +4,13 @@
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#define __SIMPLE_DEVICE__
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#include <arch/romstage.h>
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#include <commonlib/helpers.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/smm.h>
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#include <device/pci_ops.h>
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#include <cbmem.h>
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#include <security/intel/txt/txt_platform.h>
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#include <security/intel/txt/txt_register.h>
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#include <types.h>
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#include "haswell.h"
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@ -19,9 +19,9 @@ static uintptr_t northbridge_get_tseg_base(void)
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return ALIGN_DOWN(pci_read_config32(HOST_BRIDGE, TSEG), 1 * MiB);
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}
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static size_t northbridge_get_tseg_size(void)
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static uintptr_t northbridge_get_tseg_limit(void)
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{
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return CONFIG_SMM_TSEG_SIZE;
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return ALIGN_DOWN(pci_read_config32(HOST_BRIDGE, BGSM), 1 * MiB);
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}
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union dpr_register txt_get_chipset_dpr(void)
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@ -62,7 +62,9 @@ void *cbmem_top_chipset(void)
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void smm_region(uintptr_t *start, size_t *size)
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{
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*start = northbridge_get_tseg_base();
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*size = northbridge_get_tseg_size();
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*size = northbridge_get_tseg_limit();
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*size -= *start;
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}
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void fill_postcar_frame(struct postcar_frame *pcf)
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