soc/intel/elkhartlake: Make PCIe root port max payload size configurable

The data payload size of PCIe root ports can be set to either 128
(default) or 256 bytes. A bigger payload size can improve PCIe data
throughput on the given port. FSP-S provides a parameter to configure
this value.

This patch provides a chip config so that this FSP parameter can be set
as needed in the devicetree on mainboard level.

Change-Id: I5798a72adaa8089dda0b4bc12266b5a235ed4aa3
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>

src/soc/intel/elkhartlake/chip.h

@@ -240,6 +240,12 @@ struct soc_intel_elkhartlake_config {
 	/* PCIe RP L1 substate */
 	enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS];
 
+	/* PCIe root port maximum payload size, default is set to 128 bytes. */
+	enum {
+		RpMaxPayload_128,
+		RpMaxPayload_256,
+	} PcieRpMaxPayload[CONFIG_MAX_ROOT_PORTS];
+
 	/* PCIe root port speed. 0: Auto (Default); 1: Gen1; 2: Gen2; 3: Gen3 */
 	uint8_t PcieRpPcieSpeed[CONFIG_MAX_ROOT_PORTS];
 

src/soc/intel/elkhartlake/fsp_params.c

@@ -388,6 +388,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 		params->PcieRpVc1TcMap[i] = 0x60;
 		if (config->realtime_tuning_enable)
 			params->PcieRpEnableCpm[i] = 0;
+		params->PcieRpMaxPayload[i] = config->PcieRpMaxPayload[i];
 	}
 
 	/* SATA config */