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mainboard/google/zoombini/variants/meowth: configure FP MCU SPI device 

Configure the FP MCU interface on GSPI1.

BRANCH=none
BUG=b:71986991
TEST=boot on reworked Meowth with a ZerbleBarn board attached to
GSPI1 and see the cros_ec kernel driver detecting it.

Change-Id: Ib874ddaf4948a766fd05c11f4675dbfdb679059d
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://review.coreboot.org/23328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Vincent Palatin 2018-01-15 14:21:06 +01:00 committed by Patrick Georgi
parent 7c7181fc96
commit f5c416c044
2 changed files with 10 additions and 1 deletions
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1
src/mainboard/google/zoombini/Kconfig
View File

@ -3,6 +3,7 @@ config BOARD_GOOGLE_BASEBOARD_ZOOMBINI
def_bool n def_bool n
select BOARD_ROMSIZE_KB_16384 select BOARD_ROMSIZE_KB_16384
select DRIVERS_I2C_GENERIC select DRIVERS_I2C_GENERIC
select DRIVERS_SPI_ACPI
select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_LPC select EC_GOOGLE_CHROMEEC_LPC
select HAVE_ACPI_TABLES select HAVE_ACPI_TABLES

10
src/mainboard/google/zoombini/variants/meowth/devicetree.cb
View File

@ -98,7 +98,15 @@ chip soc/intel/cannonlake
device pci 1e.0 on end # UART #0 device pci 1e.0 on end # UART #0
device pci 1e.1 off end # UART #1 device pci 1e.1 off end # UART #1
device pci 1e.2 on end # GSPI #0 device pci 1e.2 on end # GSPI #0
device pci 1e.3 on end # GSPI #1 device pci 1e.3 on
chip drivers/spi/acpi
register "hid" = "ACPI_DT_NAMESPACE_HID"
register "uid" = "1"
register "compat_string" = ""google,cros-ec-spi""
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A22_IRQ)"
device spi 0 on end
end
end # GSPI #1
device pci 1f.0 on device pci 1f.0 on
chip ec/google/chromeec chip ec/google/chromeec
device pnp 0c09.0 on end device pnp 0c09.0 on end